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2015-09-02drm/i915: Remove start frame argument to pipe_update_begin/end.Maarten Lankhorst3-15/+14
2015-09-02drm/i915: guest i915 notification for Intel GVT-gZhiyuan Lv1-0/+41
2015-09-02drm/i915: Update PV INFO page definition for Intel GVT-gZhiyuan Lv1-2/+32
2015-09-02drm/i915: Always enable execlists on BDW for vgpuZhiyuan Lv2-0/+13
2015-09-02drm/i915: preallocate pdps for 32 bit vgpuZhiyuan Lv2-1/+35
2015-09-02drm/i915: add yesno utility functionJani Nikula3-10/+5
2015-09-02drm/i915: move intel_hrawclk() to intel_display.cJani Nikula3-34/+34
2015-09-02drm/i915: Notify GuC rc6 stateAlex Dai1-0/+15
2015-09-02drm/i915/guc: Support GuC version 4.3Alex Dai2-14/+14
2015-09-02drm/i915: Fix module initialisation, v2.Maarten Lankhorst3-18/+7
2015-09-01drm/i915: Factor out intel_crtc_has_encoders()Ville Syrjälä1-9/+13
2015-09-01drm/i915: Fix clock readout when pipes are enabled w/o portsVille Syrjälä1-0/+8
2015-09-01drm/i915: Add CHV PHY LDO power sanity checksVille Syrjälä2-17/+111
2015-09-01drm/i915: Add some CHV DPIO lane power state assertsVille Syrjälä2-0/+62
2015-09-01drm/i915: Clean up CHV lane soft reset programmingVille Syrjälä2-82/+100
2015-09-01drm/i915: Bump command parser version number.Francisco Jerez1-1/+2
2015-09-01drm/i915/dp: use the drm dp helper for determining sink tps3 supportJani Nikula1-2/+1
2015-09-01drm/dp: add drm_dp_tps3_supported helperJani Nikula1-0/+7
2015-08-28drm/i915: Update DRIVER_DATE to 20150828Daniel Vetter1-1/+1
2015-08-26Partially revert "drm/i915: Use full atomic modeset."Maarten Lankhorst3-1/+7
2015-08-26drm/i915: gen 9 can check for unclaimed registers tooPaulo Zanoni2-0/+8
2015-08-26drm/i915: Force CL2 off in CHV x1 PHYVille Syrjälä2-0/+10
2015-08-26drm/i915: Enable DPIO SUS clock gating on CHVVille Syrjälä2-1/+6
2015-08-26drm/i915: Force common lane on for the PPS kick on CHVVille Syrjälä1-3/+13
2015-08-26drm/i915: Trick CL2 into life on CHV when using pipe B with port BVille Syrjälä4-0/+78
2015-08-26drm/i915: Implement PHY lane power gating for CHVVille Syrjälä5-59/+221
2015-08-26drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enableVille Syrjälä1-21/+24
2015-08-26drm/i915: Make some string arrays constVille Syrjälä1-2/+2
2015-08-26drm/i915: Use ARRAY_SIZE() instead of hand rolling itVille Syrjälä3-4/+3
2015-08-26drm/i915: Fix some gcc warningsVille Syrjälä1-2/+2
2015-08-26drm/i915/bxt: Use correct live status register for BXT platformJani Nikula1-0/+25
2015-08-26drm/i915: split g4x_digital_port_connected to g4x and vlv variantsJani Nikula1-31/+39
2015-08-26drm/i915: split ibx_digital_port_connected to ibx and cpt variantsJani Nikula1-35/+43
2015-08-26drm/i915: add common intel_digital_port_connected functionJani Nikula1-19/+22
2015-08-26drm/i915: add MISSING_CASE annotation to ibx_digital_port_connectedJani Nikula1-2/+8
2015-08-26drm/i915: make g4x_digital_port_connected return boolean statusJani Nikula1-15/+11
2015-08-26drm/i915: move ibx_digital_port_connected to intel_dp.cJani Nikula3-55/+53
2015-08-26drm/i915: DVO pixel clock checkMika Kahola1-0/+7
2015-08-26drm/i915: DSI pixel clock checkMika Kahola1-0/+3
2015-08-26drm/i915: LVDS pixel clock checkMika Kahola1-0/+3
2015-08-26drm/i915: Store max dotclockMika Kahola2-0/+21
2015-08-26drm/i915: Add vlv_dport_to_phy()Ville Syrjälä1-2/+16
2015-08-26drm/i915: Move VLV/CHV prepare_pll laterVille Syrjälä1-9/+5
2015-08-26drm/i915: Add locking around chv_phy_control_init()Ville Syrjälä1-0/+2
2015-08-26drm/i915: Move DPIO port init earlierVille Syrjälä2-22/+20
2015-08-26drm/i915: Add encoder->post_pll_disable() hooks and move CHV clock buffer dis...Ville Syrjälä4-11/+51
2015-08-26drm/i915: Always program unique transition scale for CHVVille Syrjälä2-41/+42
2015-08-26drm/i915: Always program m2 fractional value on CHVVille Syrjälä1-2/+1
2015-08-26drm/i915: fix driver's versions of WARN_ON & WARN_ON_ONCEDave Gordon1-2/+2
2015-08-26drm/i915: Put back lane_count into intel_dp and add link_rate tooVille Syrjälä4-31/+33
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