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2016-09-07clk: bcm2835: Skip PLLC clocks when deciding on a new clock parentEric Anholt1-0/+23
2016-09-07clk: bcm2835: Mark the CM SDRAM clock's parent as criticalEric Anholt1-0/+25
2016-09-07clk: bcm2835: Mark GPIO clocks enabled at boot as criticalEric Anholt1-1/+9
2016-09-07clk: bcm2835: Mark the VPU clock as criticalEric Anholt1-1/+4
2016-09-07MAINTAINERS: Add section for Renesas clock driversGeert Uytterhoeven1-0/+6
2016-09-04clk: rockchip: use the dclk_vop_frac clock ids on rk3399Yakir Yang1-2/+2
2016-09-04clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividersDouglas Anderson1-13/+13
2016-09-04clk: rockchip: add 2016M to big cpu clk rate table on rk3399Shunqian Zheng1-0/+1
2016-09-04clk: rockchip: add rk3399 ddr clock supportLin Huang1-0/+19
2016-09-04clk: rockchip: add dclk_vop_frac ids for rk3399 vopYakir Yang1-0/+2
2016-09-03clk: meson-gxbb: Export PWM related clocks for DTNeil Armstrong2-3/+6
2016-09-02meson: clk: Add support for clock gatesAlexander Müller2-0/+254
2016-09-02gxbb: clk: Adjust MESON_GATE macro to be shared with meson8bAlexander Müller2-85/+85
2016-09-02clk: meson: Copy meson8b CLKID defines to private header fileAlexander Müller3-3/+107
2016-09-02meson: clk: Rename register names according to Amlogic datasheetAlexander Müller2-19/+18
2016-09-02meson: clk: Move register definitions to meson8b.hAlexander Müller2-16/+41
2016-09-02clk: meson: Rename meson8b-clkc.c to reflect gxbb naming conventionAlexander Müller2-1/+1
2016-09-01clk: rockchip: add new clock-type for the ddrclkLin Huang4-0/+197