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2023-04-06drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layoutDmitry Baryshkov2-12/+2
The pipe's layout is not cached, corresponding data structure is zeroed out each time in the dpu_plane_sspp_atomic_update(), right before the call to _dpu_plane_set_scanout() -> dpu_format_populate_layout(). Drop plane_addr comparison against previous layout and corresponding EAGAIN handling. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/527314/ Link: https://lore.kernel.org/r/20230316161653.4106395-5-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-04-06drm/msm/dpu: move SSPP debugfs creation to dpu_kms.cDmitry Baryshkov3-17/+18
As SSPP blocks are now visible through dpu_kms->rm.sspp_blocks, move SSPP debugfs creation from dpu_plane to dpu_kms. We are going to break the 1:1 correspondence between planes and SSPPs, so it makes no sense anymore to create SSPP debugfs entries in dpu_plane.c Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/527317/ Link: https://lore.kernel.org/r/20230316161653.4106395-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-04-06drm/msm/dpu: move SSPP allocation to the RMDmitry Baryshkov3-13/+38
Follow the example of all other hw blocks and initialize SSPP blocks in Resource Manager. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/527313/ Link: https://lore.kernel.org/r/20230316161653.4106395-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-04-06drm/msm/dpu: rename struct dpu_hw_pipe(_cfg) to dpu_hw_sspp(_cfg)Dmitry Baryshkov3-60/+62
For all hardware blocks except SSPP the corresponding struct is named after the block. Rename dpu_hw_pipe (SSPP structure) to dpu_hw_sspp. Also rename struct dpu_hw_pipe_cfg to dpu_hw_sspp_cfg to follow this change. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/527312/ Link: https://lore.kernel.org/r/20230316161653.4106395-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-04-06drm/msm/dpu: Add support for AR30 formatLeonard Lausen3-0/+14
Commit da7716a249b699978fb5 ("drm/msm/dpu: Add support for XR30 format") enabled support for the 10-bit XR30 color format but missed enabling support for the corresponding per-pixel alpha-blending AR30 color format. Declaring only XR30 but not AR30 color format support can trigger bugs in userspace. KDE KWin compositor versions prior to 5.27.3 for example prefer 10-bit color formats, rendering a 1cm^2 black box around the cursor due to missing per-pixel alpha-blending. Signed-off-by: Leonard Lausen <leonard@lausen.nl> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> # Trogdor (sc7180) Patchwork: https://patchwork.freedesktop.org/patch/527985/ Link: https://lore.kernel.org/r/6f33219dc848ccd7122bce6933338033aa18c33c@lausen.nl Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-04-06drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280Kalyan Thota5-7/+58
Flush mechanism for DSPP blocks has changed in sc7280 family, it allows individual sub blocks to be flushed in coordination with master flush control. Representation: master_flush && (PCC_flush | IGC_flush .. etc ) This change adds necessary support for the above design. Changes in v1: - Few nits (Doug, Dmitry) - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry) Changes in v2: - Move the address offset to flush macro (Dmitry) - Separate ops for the sub block flush (Dmitry) Changes in v3: - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry) Changes in v4: - Use shorter version for unsigned int (Stephen) Changes in v5: - Spurious patch please ignore. Changes in v6: - Add SOB tag (Doug, Dmitry) Changes in v7: - Cache flush mask per dspp (Dmitry) - Few nits (Marijn) Changes in v8: - Few nits (Marijn) Changes in v9: - Use DSPP enum while accessing flush mask to make it readable (Dmitry) - Few nits (Dmitry) Changes in v10: - Fix white spaces in a separate patch (Dmitry) Changes in v11: - Define a macro for dspp flush selection (Marijn) - Few nits (Marijn) Changes in v12: - Minor comments (reorder macros and a condition) (Marijn) Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com> Tested-by: Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/520701/ Link: https://lore.kernel.org/r/1674814487-2112-1-git-send-email-quic_kalyant@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>