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* ARM: OMAP: Make OMAP clocksource source selection using kernel paramVaibhav Hiremath2012-05-094-77/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current OMAP code supports couple of clocksource options based on compilation flag (CONFIG_OMAP_32K_TIMER). The 32KHz sync-timer and a gptimer which can run on 32KHz or system clock (e.g 38.4 MHz). So there can be 3 options - 1. 32KHz sync-timer 2. Sys_clock based (e.g 13/19.2/26/38.4 MHz) gptimer 3. 32KHz based gptimer. The optional gptimer based clocksource was added so that it can give the high precision than sync-timer, so expected usage was 2 and not 3. Unfortunately option 2, clocksource doesn't meet the requirement of free-running clock as per clocksource need. It stops in low power states when sys_clock is cut. That makes gptimer based clocksource option useless for OMAP2/3/4 devices with sys_clock as a clock input. So, in order to use option 2, deeper idle state MUST be disabled. Option 3 will still work but it is no better than 32K sync-timer based clocksource. We must support both sync timer and gptimer based clocksource as some OMAP based derivative SoCs like AM33XX does not have the sync timer. Considering above, make sync-timer and gptimer clocksource runtime selectable so that both OMAP and AMXXXX continue to use the same code. And, in order to precisely configure/setup sched_clock for given clocksource, decision has to be made early enough in boot sequence. So, the solution is, Use standard kernel parameter ("clocksource=") to override default 32k_sync-timer, in addition to this, we also use hwmod database lookup mechanism, through which at run-time we can identify availability of 32k-sync timer on the device, else fall back to gptimer. Also, moved low-level SoC specific init code to respective files, (mach-omap1/timer32k.c and mach-omap2/timer.c) Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tarun Kanti DebBarma <tarun.kanti@ti.com> Cc: Ming Lei <tom.leiming@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2+: Replace space with underscore in the name field of system timersVaibhav Hiremath2012-05-091-3/+3
| | | | | | | | | | | | | | | | | | | | | Depending on the bootloader, passing command-line arguments with spaces may have issues. Some bootloaders doesn't seem to pass along the quotes, passing only 'gp' part of the string, which leads to wrong override configuration. The only affected kernel parameter configuration for OMAP family is "clocksource=", used to override kernel clocksource. So this patch changes "gp timer" => "gp_timer", for clockevent, clocksource and timer irq_handler. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP1: Add checks for possible error condition in timer_initVaibhav Hiremath2012-05-093-20/+18
| | | | | | | | | | | | | | | | | | On OMAP1, omap_32k_timer_init() function always returns "true", irrespective of whether error occurred while initializing 32k sync counter as a kernel clocksource or not and execution will never fallback to mpu_timer clocksource init code. This patch adds check for return value from function omap_init_clocksource_32k(), and fallback to omap_mpu_timer_init() in case of failure/error from omap_init_clocksource_32k(). Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge tag 'omap-devel-c-for-3.5' of ↵Tony Lindgren2012-05-0916-31/+562
|\ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-hwmod-data Some OMAP IP block data additions for 3.5, along with a fix for a longstanding watchdog timer integration problem.
| * ARM: OMAP2+: WDTIMER integration: fix !PM boot crash, disarm timer after ↵Kevin Hilman2012-05-096-20/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hwmod reset Without runtime PM enabled, hwmod needs to leave all IP blocks in an enabled state by default so any driver access to the HW will succeed. This is accomplished by seting the postsetup_state to enabled for all hwmods during init when runtime PM is disabled. Currently, we have a special case for WDT in that its postsetup_state is always set to disabled. This is done so that the WDT is disabled and the timer is disarmed at boot in case there is no WDT driver. This also means that when runtime PM is disabled, if a WDT driver *is* built in the kernel, the kernel will crash on the first access to the WDT hardware. We can't simply leave the WDT module enabled, because the timer is armed by default after reset. That means that if there is no WDT driver initialzed or loaded before the timer expires, the kernel will reboot. To fix this, a custom reset method is added to the watchdog class of omap_hwmod. This method will *always* disarm the timer after hwmod reset. The WDT timer then will only be rearmed when/if the driver is loaded for the WDT. With the timer disarmed by default, we no longer need a special-case for the postsetup_state of WDT during init, so it is removed. Any platforms wishing to ensure the watchdog remains armed across the entire boot boot can simply disable the reset-on-init feature of the watchdog hwmod using omap_hwmod_no_setup_reset(). Tested on 3530/Overo, 4430/Panda. NOTE: on 4430, the hwmod OCP reset does not seem to rearm the timer as documented in the TRM (and what happens on OMAP3.) I noticed this because testing the HWMOD_INIT_NO_RESET feature with no driver loaded, I expected a reboot part way through the boot, but did not see a reboot. Adding some debug to read the counter, I verified that right after OCP softreset, the counter is not firing. After writing the magic start sequence, the timer starts counting. This means that the timer disarm sequence added here does not seem to be needed for 4430, but is technically the correct way to ensure the timer is disarmed, so it is left in for OMAP4. Special thanks to Paul Walmsley for helping brainstorm ideas to fix this problem. Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [paul@pwsan.com: updated the omap2_wd_timer_reset() function in the wake of commit 3c55c1baffa5f719eb2ae9729088bc867f972f53 ("ARM: OMAP2+: hwmod: Revert "ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status""); added kerneldoc; rolled in warning fix from Kevin] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod databaseVaibhav Hiremath2012-05-095-0/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 32k-sync timer hwmod-data and add ocp_if details to omap2 & 3 hwmod table. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP4: hwmod_data: Name the common irq for McBSP portsPeter Ujfalusi2012-05-091-4/+4
| | | | | | | | | | | | | | | | Use 'common' as name for the common irq number in hwmod data for the McBSP ports. The same name already in use for OMAP2430, and OMAP3. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP4: hwmod data: I2C: add flag for context restoreShubhrajyoti D2012-05-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Restore of context is not done for OMAP4. This patch adds the OMAP_I2C_FLAG_RESET_REGS_POSTIDLE in the OMAP4 hwmod data which activates the restore for OMAP4. Currently the OMAP4 does not hit device off still the driver may have support for it. Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Wamsley <paul@pwsan.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP3: hwmod_data: Rename the common irq for McBSP portsPeter Ujfalusi2012-05-091-5/+5
| | | | | | | | | | | | | | | | | | Use 'common' as name for the common irq number in hwmod data for the McBSP ports. The same name already in use for OMAP2430, and the OMAP4 hwmod data will be using the same name. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP2xxx: hwmod data: add HDQ/1-wire hwmodPaul Walmsley2012-05-092-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the HDQ1W hwmod for all OMAP2xxx devices. Assume that OMAP2xxx chips have the same HDQ idle handling bug as OMAP3: http://www.spinics.net/lists/linux-omap/msg63576.html and set the OCPIF_SWSUP_IDLE flag accordingly on the HDQ's OCP interface. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP3: hwmod data: add HDQ/1-wire hwmodPaul Walmsley2012-05-091-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the HDQ1W hwmod for OMAP34xx, OMAP36xx, and AM3505/3517 devices. According to the respective TRMs, it doesn't appear to be available for the 816x/814x or the AM335x. The OCPIF_SWSUP_IDLE flag is added to work around an apparent hardware bug: the hardware is not taking the CM_FCLKEN*_CORE.EN_HDQ bit into account when considering whether to go idle: http://www.spinics.net/lists/linux-omap/msg63576.html This causes HDQ transfers to fail or become corrupt. Thanks to NeilBrown for his help diagnosing and testing fixes for this problem. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de> Tested-by: NeilBrown <neilb@suse.de>
| * ARM: OMAP2+: hwmod data: add HDQ/1-wire hwmod shared dataPaul Walmsley2012-05-093-0/+35
| | | | | | | | | | | | | | | | | | | | Much of the HDQ1W integration data is common between multiple generations of OMAP SoCs, so rather than make several copies, we add it once into files which are compiled for multiple SoCs. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de> Tested-by: NeilBrown <neilb@suse.de>
| * ARM: OMAP2+: HDQ1W: add custom reset functionPaul Walmsley2012-05-093-1/+109
| | | | | | | | | | | | | | | | | | | | | | | | Implement a custom reset function for the HDQ1W IP block. This is because the HDQ1W IP block, like I2C, has an internal clock gating bit that needs to be toggled after setting the SOFTRESET bit to allow the reset to propagate. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de> Cc: Avinash.H.M <avinashhm@ti.com> Tested-by: NeilBrown <neilb@suse.de>
| * ARM: OMAP2420: hwmod data: Add MMC hwmod data for 2420Tony Lindgren2012-05-094-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MMC for 2420 so we can pass the DMA request lines the same way as we already do on omap2430 and later. Cc: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> [paul@pwsan.com: updated to apply on top of the 3.5 hwmod cleanup; changed mmc hwmod name/class to "msdi" as documented in the 2420 TRM Rev X; added sysconfig register information; added 16 bit register width flag; added MSDI custom reset code] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | Merge tag 'omap-devel-b-for-3.5' of ↵Tony Lindgren2012-05-0818-87/+97
|\| | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-prcm Some OMAP PRCM updates for 3.5. Includes some clock, clockdomain, powerdomain, PRM, and CM changes.
| *---. Merge branches 'clock_am35xx_cleanup_3.5', 'prm_cm_devel_a_3.5', ↵Paul Walmsley2012-05-0817-67/+91
| |\ \ \ | | | | | | | | | | | | | | | 'clock_devel_a_3.5' and 'pwrdm_clkdm_cleanup_3.5' into prcm_devel_a_3.5
| | | | * arm: omap3: clockdomain data: Remove superfluous commas from ↵Mark A. Greer2012-05-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gfx_sgx_3xxx_wkdeps[] Clean up clockdomains3xxx_data.c a bit by removing the superfluous commas in gfx_sgx_3xxx_wkdeps[]. Signed-off-by: Mark A. Greer <mgreer@animalcreek.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | | * ARM: OMAP2+: powerdomain: Get rid off duplicate pwrdm_clkdm_state_switch() APISantosh Shilimkar2012-05-084-16/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With patch 'ARM: OMAP2+: powerdomain: Wait for powerdomain transition in pwrdm_state_switch()', the pwrdm_clkdm_state_switch() API becomes duplicate of pwrdm_state_switch(). Get rid off duplicate pwrdm_clkdm_state_switch() and update the users of it with pwrdm_state_switch() Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | ARM: OMAP3: clock data: add clockdomain for HDQ functional clockPaul Walmsley2012-05-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the correct clockdomain for the HDQ functional clock. This is needed for the clock and hwmod PM code to work correctly. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de>
| | | * | ARM: OMAP3+: dpll: Configure autoidle mode only if it's supportedVaibhav Bedia2012-05-081-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current DPLL code enables and disables autoidle features without checking whether the autoidle register is available. Fix this by putting a check for the existence of the autoidle register in the DPLL data. With such a check in place, for DPLLs which do not support this feature, simply skipping the autoidle_reg entry in the DPLL data is sufficient. Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | ARM: OMAP2+: dmtimer: cleanup iclk usageTarun Kanti DebBarma2012-05-083-19/+1
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | We do not use iclk anywhere in the dmtimer driver and so removing it. Hence removing the timer iclk entries from OMAP4 clkdev table as well. Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | ARM: OMAP4+: Add prm and cm base init function.R Sricharan2012-05-086-21/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of statically defining seperate arrays for every OMAP4+ archs, have a generic init function to populate the arrays. This avoids the need for creating new array for every arch added in the future that reuses the prm and cm registers read/write code. Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | ARM: OMAP2/3: Add idle_st bits for ST_32KSYNC timer to prcm-common headerVaibhav Hiremath2012-05-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing idle_st bit for 32k-sync timer into the prcm-common header file, required for hwmod data. Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | ARM: OMAP3: Fix CM register bit masksRajendra Nayak2012-05-081-2/+2
| | |/ | | | | | | | | | | | | | | | | | | | | | The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL register are 3 bits wide. Fix the MASK definition accordingly. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | ARM: OMAP: clock: convert AM3517/3505 detection/flags to AM35xxKevin Hilman2012-05-082-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To improve the clarity of the code, replace the CK_3517 flag used in the clock data with CK_AM35XX. The CK_3505 flag can also be removed, since it is now unused. Acked-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | ARM: OMAP3: clock data: treat all AM35x devices the sameKevin Hilman2012-05-081-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The init for 3505/3517 specific clocks depends on the ordering of cpu_is checks, is error prone and confusing (there are 2 separate checks for cpu_is_omap3505()). Remove the 3505-specific checking since CK_3505 flag is not used, and treat all AM35x clocks the same. This means that the SGX clock (the only AM35x clkdev not currently flagged for 3505) will now be registered on 3505, but that is harmless. That can be cleaned up when the clkdev nodes are removed in favor of them being registered by hwmod. Acked-by: Vaibhav Hiremath <hvaibhav@ti.com> Tested-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | ARM: OMAP3: clock data: replace 3503/3517 flag with AM35x flag for UART4Kevin Hilman2012-05-081-1/+1
| |/ | | | | | | | | | | | | | | | | | | The AM35x UART4 is common to all AM35x devices, so use CK_AM35XX instead of (CK_3505 | CK_3517), which is equivalent. Acked-by: Vaibhav Hiremath <hvaibhav@ti.com> Tested-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | Merge tag 'omap-devel-a-for-3.5' of ↵Tony Lindgren2012-04-207-48/+1419
|\| | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-hwmod Add in most of the remaining hwmods (IP block descriptions) for the OMAP44xx family of SoCs. There still seem to be a few missing, such as those for the MMU IP blocks, but this seems to cover the bulk of the remainder.
| * ARM: OMAP4: hwmod data: add DEBUGSS skeletonBenoît Cousson2012-04-191-7/+52
| | | | | | | | | | | | | | | | | | | | Add a skeleton hwmod for the DEBUGSS and associated interconnect data. This is a basic set of data that will need further additions as further DEBUGSS information becomes available. Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP4: hwmod data: add PRCM and related IP blocksPaul Walmsley2012-04-191-5/+162
| | | | | | | | | | | | | | | | | | Add the PRCM, CM, PRM, and related hwmod and associated interconnect data. These IP blocks handle most of the on-chip power, reset, and clock control. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
| * ARM: OMAP4: hwmod data: add System Control ModulePaul Walmsley2012-04-191-4/+130
| | | | | | | | | | | | | | Add the System Control Module hwmod and associated interconnect data. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
| * ARM: OMAP4: hwmod data: add the OCP-WP IP blockBenoît Cousson2012-04-191-1/+50
| | | | | | | | | | | | | | | | | | Add the OCP-WP hwmod and associated interconnect data. The OCP-WP, or OCP watchpoint, can be used to collect interconnect data and transmit it via the STM port. Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP4: hwmod data: add OCM RAM IP blockPaul Walmsley2012-04-191-1/+31
| | | | | | | | | | | | | | | | Add the OCM RAM IP block and interconnect data. This is an oh-chip block of SRAM connected directly to the L3 bus. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
| * ARM: OMAP4: hwmod data: add remaining USB-related IP blocksBenoît Cousson2012-04-191-4/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the OCP2SCP IP block and interconnect data. The OCP2SCP can be used in conjunction with the on-chip embedded USB PHY, associated with the OTG controller. Add the on-chip full-speed USB host controller IP block and interconnect data. Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP4: hwmod data: add some interconnect-related IP blocksPaul Walmsley2012-04-192-4/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the SL2 interface IP block and interconnect data. The SL2 is related to the IVA-HD subsystem. Add IP block and interconnect data for the C2C ("Chip-to-chip") interconnect. This can provide a direct system interconnect link to other devices stacked on the OMAP package. Add the ELM IP block and interconnect data. The ELM can be used to locate errors in NAND flash connected to the GPMC. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
| * ARM: OMAP4: hwmod data: add McASPBenoît Cousson2012-04-191-1/+90
| | | | | | | | | | | | | | | | Add the McASP hwmod and associated interconnect data. The McASP is a general-purpose audio serial port. Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP4: hwmod data: add the Slimbus IP blocksBenoît Cousson2012-04-191-2/+161
| | | | | | | | | | | | | | | | | | | | | | Add the Slimbus hwmods and associated interconnect data. The Slimbus IP blocks implement a two-wire serial interface. Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP4: hwmod data: add GPUPaul Walmsley2012-04-191-1/+69
| | | | | | | | | | | | | | | | Add the GPU hwmod and associated interconnect data. The GPU is a graphics accelerator. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
| * ARM: OMAP4: hwmod data: add EMIF1 and 2Paul Walmsley2012-04-191-2/+96
| | | | | | | | | | | | | | | | Add the EMIF1 and 2 hwmods and associated interconnect data. The EMIFs are SDRAM interface IP blocks. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
| * ARM: OMAP4: hwmod data: add GPMCBenoît Cousson2012-04-191-1/+66
| | | | | | | | | | | | | | | | | | | | Add the GPMC hwmod and associated interconnect data. The GPMC is a programmable parallel-bus memory controller. Signed-off-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP4: hwmod data: add HDQ/1-wirePaul Walmsley2012-04-191-1/+60
| | | | | | | | | | | | | | | | | | Add the HDQ/1-wire hwmod and associated interconnect data. The HDQ/1-wire IP block is a low-speed serial interconnect. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Benoît Cousson <b-cousson@ti.com>
| * ARM: OMAP4: hwmod data: introduce fdif(face detect module) hwmodMing Lei2012-04-191-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add hwmod data for the OMAP4 FDIF IP block. This patch also includes a change (originally from Fernando Guzman Lugo <fernando.lugo@ti.com>) to set a softreset delay for the FDIF IP block: http://www.spinics.net/lists/arm-kernel/msg161874.html Signed-off-by: Ming Lei <ming.lei@canonical.com> Acked-by: Benoît Cousson <b-cousson@ti.com> Cc: Fernando Guzman Lugo <fernando.lugo@ti.com> [paul@pwsan.com: rearranged to match script output; fixed FDIF end address to match script data; wrote trivial changelog; combined the FDIF portion of Fernando's srst_udelay patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP2+: clockdomains: make {prm,cm}_clkdm commonPaul Walmsley2012-04-195-13/+37
| | | | | | | | | | | | | | | | | | The PRM and CM implicit clockdomains will soon be used by OMAP44xx. So, make them common to OMAP2+ and modify the OMAP4 clockdomains code so use of these clockdomains doesn't crash the system. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
* | Merge tag 'omap-cleanup-b-for-3.5' of ↵Tony Lindgren2012-04-2010-7821/+5688
|\| | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into cleanup-hwmod Clean up various aspects of the OMAP hwmod code, which is the IP block control code for OMAP SoCs. In particular, this series results in a considerable diffstat savings by changing the way that IP block interconnections are defined.
| * ARM: OMAP2xxx: hwmod data: start to fix the IVA1, IVA2 and DSPPaul Walmsley2012-04-192-4/+53
| | | | | | | | | | | | | | | | | | | | | | | | N800 logs this message on boot: [ 0.182281] omap_hwmod: iva: cannot be enabled for reset (3) Fix by creating basic IVA1 and DSP hwmods for OMAP2420, and a basic IVA2 hwmod for OMAP2430. There is still more information to be added, but this should resolve the immediate issue. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP3: hwmod data: add IVA hard reset lines, main clock, clockdomainPaul Walmsley2012-04-191-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | The IVA hwmod data is missing some fields that cause the following warning on boot: [ 0.118011] omap_hwmod: iva: cannot be enabled for reset (3) Fix by encoding the IP block's main functional clock, reset lines, and clockdomain. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP3: hwmod data: fix IVA interface clockPaul Walmsley2012-04-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP3 hwmod data listed iva2_ck as an interface clock between the IVA and L3. This is incorrect. iva2_ck is not an interface clock. Since it cannot auto-idle, specifying it here prevents the IVA and at least one of the CORE clockdomains from going idle, which causes PM problems such as these upon system suspend: [ 70.626129] Powerdomain (iva2_pwrdm) didn't enter target state 1 [ 70.626190] Powerdomain (core_pwrdm) didn't enter target state 1 Fix by specifying the actual interface clock in the hwmod data. Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * ARM: OMAP2xxx: hwmod data: share common interface dataPaul Walmsley2012-04-194-518/+324
| | | | | | | | | | | | | | | | | | | | | | | | Several struct omap_hwmod_ocp_if records can be shared between OMAP2420 and OMAP2430. Move these shared records out of the chip-specific files into mach-omap2/omap_hwmod_2xxx_interconnect_data.c. This should save some memory and source lines, at the cost of readability. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com>
| * ARM: OMAP2xxx: hwmod data: share common hwmods between OMAP2420 and OMAP2430Paul Walmsley2012-04-194-1211/+740
| | | | | | | | | | | | | | | | | | | | | | | | | | After the link registration conversion, it's much easier to share some hwmod data between OMAP2420 and 2430. Move the shareable data into a common file. This should save some memory and lines of source, at the cost of readability. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com>
| * ARM: OMAP2+: hwmod data: remove forward declarations, reorganizePaul Walmsley2012-04-194-4268/+3963
| | | | | | | | | | | | | | | | | | | | | | | | | | Reorganize the hwmod data to declare the IP blocks first and the interconnects second. This allows us to remove the forward declarations, which this patch also does. Saves some lines of source data. While here, take the opportunity to synchronize the order of the OMAP44xx hwmod data with the autogenerator output -- it's slightly different due to past mismerges -- and fix a few minor typos and whitespace problems in the files. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com>
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