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| * | | MIPS: CPS: Handle cores not powering down more gracefullyPaul Burton2017-06-291-3/+24
| * | | MIPS: CPS: Prevent multi-core with dcache aliasingPaul Burton2017-06-291-3/+5
| * | | MIPS: CPS: Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6Paul Burton2017-06-291-0/+1
| * | | MIPS: CM: WARN on attempt to lock invalid VP, not BUGPaul Burton2017-06-291-1/+1
| * | | MIPS: CM: Avoid per-core locking with CM3 & higherPaul Burton2017-06-291-6/+32
| * | | MIPS: Skip IPI setup if we only have 1 CPUPaul Burton2017-06-291-0/+3
| * | | MIPS: Use `pr_debug' for messages from `__compute_return_epc_for_insn'Maciej W. Rozycki2017-06-291-6/+6
| * | | MIPS: math-emu: For MFHC1/MTHC1 also return SIGILL right awayMaciej W. Rozycki2017-06-291-3/+2
| * | | MIPS: Fix a typo: s/preset/present/ in r2-to-r6 emulation error messageMaciej W. Rozycki2017-06-291-1/+1
| * | | MIPS: Send SIGILL for R6 branches in `__compute_return_epc_for_insn'Maciej W. Rozycki2017-06-291-20/+15
| * | | MIPS: Send SIGILL for linked branches in `__compute_return_epc_for_insn'Maciej W. Rozycki2017-06-291-8/+4
| * | | MIPS: Rename `sigill_r6' to `sigill_r2r6' in `__compute_return_epc_for_insn'Maciej W. Rozycki2017-06-291-8/+8
| * | | MIPS: Send SIGILL for BPOSGE32 in `__compute_return_epc_for_insn'Maciej W. Rozycki2017-06-291-3/+4
| * | | MIPS: Fix unaligned PC interpretation in `compute_return_epc'Maciej W. Rozycki2017-06-291-4/+1
| * | | MIPS: Actually decode JALX in `__compute_return_epc_for_insn'Maciej W. Rozycki2017-06-291-0/+1
| * | | MIPS: math-emu: Prevent wrong ISA mode instruction emulationMaciej W. Rozycki2017-06-291-0/+38
| * | | MIPS: Use queued spinlocks (qspinlock)Paul Burton2017-06-294-232/+4
| * | | MIPS: Use queued read/write locks (qrwlock)Paul Burton2017-06-294-224/+4
| * | | MIPS: cmpxchg: Rearrange __xchg() arguments to match xchg()Paul Burton2017-06-291-2/+3
| * | | MIPS: cmpxchg: Implement 1 byte & 2 byte cmpxchg()Paul Burton2017-06-292-0/+64
| * | | MIPS: cmpxchg: Implement 1 byte & 2 byte xchg()Paul Burton2017-06-293-3/+60
| * | | MIPS: cmpxchg: Implement __cmpxchg() as a functionPaul Burton2017-06-291-27/+32
| * | | MIPS: cmpxchg: Drop __xchg_u{32,64} functionsPaul Burton2017-06-291-31/+17
| * | | MIPS: cmpxchg: Error out on unsupported xchg() callsPaul Burton2017-06-291-15/+17
| * | | MIPS: cmpxchg: Use __compiletime_error() for bad cmpxchg() pointersPaul Burton2017-06-291-3/+10
| * | | MIPS: cmpxchg: Pull xchg() asm into a macroPaul Burton2017-06-291-48/+33
| * | | MIPS: cmpxchg: Unify R10000_LLSC_WAR & non-R10000_LLSC_WAR casesPaul Burton2017-06-291-58/+22
| * | | MIPS: unaligned: Add DSP lwx & lhx missaligned access supportMiodrag Dinic2017-06-292-74/+111
| * | | MIPS: R6: Fix PREF instruction usage by memcpy for MIPS R6Leonid Yegoshin2017-06-291-0/+3
| * | | MIPS: build: Fix "-modd-spreg" switch usage when compiling for mips32r6Miodrag Dinic2017-06-291-1/+1
| * | | MIPS: cmdline: Add support for 'memmap' parameterMiodrag Dinic2017-06-291-0/+40
| * | | MIPS: Loogson: Make enum loongson_cpu_type more clearHuacai Chen2017-06-292-9/+24
| * | | MIPS: Loongson-3: support irq_set_affinity() in i8259 chipHuacai Chen2017-06-291-13/+54
| * | | MIPS: Loongson-3: IRQ balancing for PCI devicesHuacai Chen2017-06-292-3/+34
| * | | MIPS: Loongson: Add NMI handler supportHuacai Chen2017-06-291-0/+13
| * | | MIPS: Loongson: Add Loongson-3A R3 basic supportHuacai Chen2017-06-284-2/+11
| * | | MIPS: SEAD-3: Fix GIC interrupt specifiersPaul Burton2017-06-281-4/+4
| * | | MIPS: SEAD-3: Set interrupt-parent per-device, not at root nodePaul Burton2017-06-282-7/+24
| * | | MIPS: generic: Set RTC_ALWAYS_BCD to 0Paul Burton2017-06-281-1/+1
| * | | MIPS: generic: Abstract FDT fixup applicationPaul Burton2017-06-283-22/+69
| * | | MIPS: generic/yamon-dt: Use serial* rather than uart* aliasesPaul Burton2017-06-282-5/+5
| * | | MIPS: generic/yamon-dt: Support > 256MB of RAMPaul Burton2017-06-283-25/+106
| * | | MIPS: generic/yamon-dt: Pull YAMON DT shim code out of SEAD-3 boardPaul Burton2017-06-285-174/+251
| * | | MIPS: SEAD-3: Remove GIC timer from DTPaul Burton2017-06-281-5/+0
| * | | MIPS: Branch straight to ll in mips_atomic_set()James Hogan2017-06-281-5/+1
| * | | MIPS: Fix mips_atomic_set() with EVAJames Hogan2017-06-281-2/+5
| * | | MIPS: Save static registers before sysmipsJames Hogan2017-06-285-4/+10
| * | | MIPS: Fix mips_atomic_set() retry conditionJames Hogan2017-06-281-1/+1
| * | | MIPS: perf: add I6500 handlingMarcin Nowakowski2017-06-281-4/+10
| * | | MIPS: Probe the I6500 CPUPaul Burton2017-06-284-1/+10
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