| Commit message (Expand) | Author | Age | Files | Lines |
* | MIPS: OCTEON: irq: add CIB and other fixes | David Daney | 2015-02-20 | 1 | -269/+780 |
* | MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs. | David Daney | 2015-02-20 | 1 | -2/+43 |
* | MIPS: OCTEON: More OCTEONIII support | Chandrakala Chavva | 2015-02-20 | 4 | -2/+326 |
* | MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits. | Chad Reese | 2015-02-20 | 1 | -20/+0 |
* | MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup. | David Daney | 2015-02-20 | 2 | -6/+17 |
* | MIPS: OCTEON: Update octeon-model.h code for new SoCs. | David Daney | 2015-02-20 | 5 | -27/+90 |
* | MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX | David Daney | 2015-02-20 | 3 | -4/+8 |
* | MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h | David Daney | 2015-02-20 | 1 | -30/+105 |
* | MIPS: OCTEON: Implement the core-16057 workaround | David Daney | 2015-02-20 | 1 | -0/+22 |
* | MIPS: OCTEON: Delete unused COP2 saving code | Aleksey Makarov | 2015-02-20 | 1 | -26/+0 |
* | MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register | Chandrakala Chavva | 2015-02-20 | 1 | -3/+3 |
* | MIPS: OCTEON: Save and restore CP2 SHA3 state | David Daney | 2015-02-20 | 3 | -11/+35 |
* | MIPS: OCTEON: Fix FP context save. | David Daney | 2015-02-20 | 1 | -12/+7 |
* | MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs | David Daney | 2015-02-20 | 4 | -32/+150 |
* | MIPS: boot: Provide more uImage options | Markos Chandras | 2015-02-20 | 2 | -2/+55 |
* | MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h | David Daney | 2015-02-20 | 1 | -6/+0 |
* | MIPS: ip22-gio: Remove legacy suspend/resume support | Lars-Peter Clausen | 2015-02-20 | 2 | -26/+0 |
* | mips: pci: Add ifdef around pci_proc_domain | Zubair Lutfullah Kakakhel | 2015-02-20 | 1 | -0/+2 |
* | MIPS: Alchemy: Fix cpu clock calculation | Manuel Lauss | 2015-02-20 | 1 | -0/+2 |
* | MIPS: Alchemy: remove declaration for set_cpuspec | Manuel Lauss | 2015-02-20 | 1 | -1/+0 |
* | MIPS: Alchemy: preset loops_per_jiffy based on CPU clock | Manuel Lauss | 2015-02-20 | 2 | -0/+9 |
* | MIPS: Alchemy: fix Au1000/Au1500 LRCLK calculation | Manuel Lauss | 2015-02-20 | 1 | -5/+14 |
* | MIPS: Add set/clear CP0 macros for PageGrain register | Steven J. Hill | 2015-02-20 | 3 | -4/+5 |
* | MIPS: Usage and cosmetic cleanups of page table bits. | Steven J. Hill | 2015-02-19 | 2 | -62/+38 |
* | Merge branch 'mipsr6-for-3.20' of git://git.linux-mips.org/pub/scm/mchandras/... | Ralf Baechle | 2015-02-19 | 65 | -415/+4405 |
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| * | MIPS: Add Malta QEMU 32R6 defconfig | Markos Chandras | 2015-02-17 | 1 | -0/+193 |
| * | MIPS: Malta: Add support for building MIPS R6 kernel | Markos Chandras | 2015-02-17 | 1 | -0/+2 |
| * | MIPS: kernel: elf: Improve the overall ABI and FPU mode checks | Markos Chandras | 2015-02-17 | 3 | -132/+194 |
| * | MIPS: asm: fpu: Allow 64-bit FPU on MIPS32 R6 | Markos Chandras | 2015-02-17 | 1 | -1/+2 |
| * | MIPS: kernel: process: Do not allow FR=0 on MIPS R6 | Markos Chandras | 2015-02-17 | 1 | -0/+4 |
| * | MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as well | Markos Chandras | 2015-02-17 | 2 | -5/+6 |
| * | MIPS: Make use of the ERETNC instruction on MIPS R6 | Markos Chandras | 2015-02-17 | 5 | -4/+28 |
| * | MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6 | Leonid Yegoshin | 2015-02-17 | 8 | -5/+2518 |
| * | MIPS: asm: mipsregs: Add support for the LLADDR register | Markos Chandras | 2015-02-17 | 1 | -0/+2 |
| * | MIPS: Add LLB bit and related feature for the Config 5 CP0 register | Markos Chandras | 2015-02-17 | 4 | -0/+7 |
| * | MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructions | Markos Chandras | 2015-02-17 | 3 | -1/+20 |
| * | MIPS: Emulate the new MIPS R6 BEQZC and JIC instructions | Markos Chandras | 2015-02-17 | 3 | -1/+16 |
| * | MIPS: Emulate the new MIPS R6 BALC instruction | Markos Chandras | 2015-02-17 | 3 | -1/+19 |
| * | MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructions | Markos Chandras | 2015-02-17 | 3 | -2/+7 |
| * | MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions | Markos Chandras | 2015-02-17 | 3 | -1/+21 |
| * | MIPS: Emulate the new MIPS R6 branch compact (BC) instruction | Markos Chandras | 2015-02-17 | 3 | -1/+23 |
| * | MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructions | Markos Chandras | 2015-02-17 | 2 | -0/+47 |
| * | MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructions | Markos Chandras | 2015-02-17 | 2 | -0/+55 |
| * | MIPS: Emulate the BC1{EQ,NE}Z FPU instructions | Markos Chandras | 2015-02-17 | 3 | -30/+101 |
| * | MIPS: kernel: branch: Do not emulate the branch likelies on MIPS R6 | Markos Chandras | 2015-02-17 | 2 | -13/+89 |
| * | MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6 | Markos Chandras | 2015-02-17 | 3 | -2/+15 |
| * | MIPS: mm: scache: Add secondary cache support for MIPS R6 cores | Markos Chandras | 2015-02-17 | 2 | -2/+4 |
| * | MIPS: mm: c-r4k: Set the correct ISA level | Markos Chandras | 2015-02-17 | 1 | -1/+1 |
| * | MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction | Leonid Yegoshin | 2015-02-17 | 1 | -3/+3 |
| * | MIPS: mm: page: Add MIPS R6 support | Markos Chandras | 2015-02-17 | 1 | -4/+26 |