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* powerpc/mm: Add hooks for cxlIan Munsie2014-10-082-1/+7
| | | | | | | | | | | | | | | | | | | | | | | This adds hooks into the core powerpc mm code for cxl. The core powerpc code sometimes uses local tlbie. Unfortunately this won't work with the current cxl driver as it relies on snooping tlbie broadcasts. The cxl hardware can have TLB entries invalidated via MMIO but this is not currently supported by the driver. In future we can make local tlbie smarter so that it invalidates cxl contexts via MMIO when it needs to but for now we have this workaround. This workaround checks for any active cxl contexts and if so, disables local tlbie. This also adds a hook for when SLBs are invalidated. This ensures any corresponding SLBs in cxl are also invalidated at the same time. This is required for segment demotion. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/opal: Add PHB to cxl mode callIan Munsie2014-10-082-0/+3
| | | | | | | | This adds the OPAL call to change a PHB into cxl mode. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/mm: Add new hash_page_mm()Ian Munsie2014-10-082-7/+18
| | | | | | | | | | | | | | This adds a new function hash_page_mm() based on the existing hash_page(). This version allows any struct mm to be passed in, rather than assuming current. This is useful for servicing co-processor faults which are not in the context of the current running process. We need to be careful here as the current hash_page() assumes current in a few places. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/powerpc: Add new PCIe functions for allocating cxl interruptsIan Munsie2014-10-082-0/+185
| | | | | | | | This adds a number of functions for allocating IRQs under powernv PCIe for cxl. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/powernv: Split out set MSI IRQ chip codeIan Munsie2014-10-081-18/+24
| | | | | | | | | | | Some of the MSI IRQ code in pnv_pci_ioda_msi_setup() is generically useful so split it out. This will be used by some of the cxl PCIe code later. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/mm: Export mmu_kernel_ssize and mmu_linear_psizeIan Munsie2014-10-081-0/+2
| | | | | | | | | Export mmu_kernel_ssize and mmu_linear_psize. These are needed by the cxl driver which has it's own MMU. To setup the MMU cxl needs access to these. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/msi: Improve IRQ bitmap allocatorIan Munsie2014-10-081-11/+25
| | | | | | | | | | | | | | | | | | Currently msi_bitmap_alloc_hwirqs() will round up any IRQ allocation requests to the nearest power of 2. eg. ask for 5 IRQs and you'll get 8. This wastes a lot of IRQs which can be a scarce resource. For cxl we may require multiple IRQs for every context that is attached to the accelerator. There may be 1000s of contexts attached, hence we can easily run out of IRQs, especially if we are needlessly wasting them. This changes the msi_bitmap_alloc_hwirqs() to allocate only the required number of IRQs, hence avoiding this wastage. It keeps the natural alignment requirement though. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/cell: Make spu_flush_all_slbs() genericIan Munsie2014-10-084-14/+21
| | | | | | | | | | This moves spu_flush_all_slbs() into a generic call copro_flush_all_slbs(). This will be useful when we add cxl which also needs a similar SLB flush call. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/cell: Move data segment faulting code out of cell platformIan Munsie2014-10-085-49/+69
| | | | | | | | | | | | | | | | | | __spu_trap_data_seg() currently contains code to determine the VSID and ESID required for a particular EA and mm struct. This code is generically useful for other co-processors. This moves the code of the cell platform so it can be used by other powerpc code. It also adds 1TB segment handling which Cell didn't support. The new function is called copro_calculate_slb(). This also moves the internal struct spu_slb to a generic struct copro_slb which is now used in the Cell and copro code. We use this new struct instead of passing around esid and vsid parameters. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/cell: Move spu_handle_mm_fault() out of cell platformIan Munsie2014-10-088-14/+33
| | | | | | | | | | | | | Currently spu_handle_mm_fault() is in the cell platform. This code is generically useful for other non-cell co-processors on powerpc. This patch moves this function out of the cell platform into arch/powerpc/mm so that others may use it. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/pseries: Use new defines when calling H_SET_MODEMichael Neuling2014-10-071-6/+6
| | | | | | | | Now that we define these in the KVM code, use these defines when we call H_SET_MODE. No functional change. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/perf/hv-24x7: Simplify catalog_read()sukadev@linux.vnet.ibm.com2014-10-071-87/+14
| | | | | | | | | | | | | | | | | catalog_read() implements the read interface for the sysfs file /sys/bus/event_source/devices/hv_24x7/interface/catalog It essentially takes a buffer, an offset and count as parameters to the read() call. It makes a hypervisor call to read a specific page from the catalog and copy the required bytes into the given buffer. Each call to catalog_read() returns at most one 4K page. Given these requirements, we should be able to simplify the catalog_read(). Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/perf/hv-24x7: use kmem_cache instead of aligned stack allocationsCody P Schafer2014-10-071-18/+37
| | | | | | | | | | | | | Ian pointed out the use of __aligned(4096) caused rather large stack consumption in single_24x7_request(), so use the kmem_cache hv_page_cache (which we've already got set up for other allocations) insead of allocating locally. CC: Haren Myneni <hbabu@us.ibm.com> Reported-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Cody P Schafer <dev@codyps.com> Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/powernv: Fix endian bug in LPC bus debugfs accessorsBenjamin Herrenschmidt2014-10-071-1/+3
| | | | | | | | | | When reading from the LPC, the OPAL FW calls return the value via pointer to a uint32_t which is always returned big endian. Our internal inb/outb implementation byteswaps that fine but our debugfs code is still broken. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> CC: <stable@vger.kernel.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* Merge branch 'next' of ↵Michael Ellerman2014-10-0425-201/+580
|\ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git Freescale updates from Scott (27 commits): "Highlights include DMA32 zone support (SATA, USB, etc now works on 64-bit FSL kernels), MSI changes, 8xx optimizations and cleanup, t104x board support, and PrPMC PCI enumeration."
| * Revert "powerpc/fsl_msi: spread msi ints across different MSIRs"Scott Wood2014-09-194-52/+11
| | | | | | | | | | | | | | | | | | | | This reverts commit c822e73731fce3b49a4887140878d084d8a44c08. This commit conflicted with a bitmap allocator change that partially accomplishes the same thing, but which does so more correctly. Revert this one until it can be respun on top of the correct change. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/mm: Use common paging_init() for NUMAScott Wood2014-09-192-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1c98025c6c95bc057a25e2c6596de23288c68160 "powerpc: Dynamic DMA zone limits" updated how zones are created in paging_init(), but missed the NUMA version of paging_init(). This was noticed via a linker error, since dma_pfn_limit_to_zone() was, like the non-NUMA paging_init(), limited by #ifndef CONFIG_NEED_MULTIPLE_NODES. It turns out that the NUMA paging_init() was not actually doing anything different from the standard paging_init(), other than a couple debug prints, a couple 32-bit-only ifdef sections, and a call to mark_nonram_nosave(). It's not clear whether mark_nonram_nosave() is inherently wrong to do for NUMA, or just not useful on targets that have NUMA, but for now I'm preserving the existing behavior. Fixes: 1c98025c6c9 "powerpc: Dynamic DMA zone limits" Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/85xx/defconfig: Remove duplicate CONFIG_RTC_DRV_DS1307Scott Wood2014-09-192-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Commit a95e8c28b3dc "powerpc/defconfig: update RTC support" duplicated the CONFIG_RTC_DRV_DS1307 symbol in mpc85xx_defconfig and mpc85xx_smp_defconfig, resulting in this: arch/powerpc/configs/mpc85xx_smp_defconfig:217:warning: override: reassigning to symbol RTC_DRV_DS1307 Fixes: a95e8c28b3dc "powerpc/defconfig: update RTC support" Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc: dts: t208x: Change T208x USB controller versionNikhil Badola2014-09-171-2/+2
| | | | | | | | | | | | | | Change USB controller version to 2.5 in compatible string for T2080/T2081 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl-booke64: add missing virtualization options in defconfigTudor Laurentiu2014-09-101-36/+8
| | | | | | | | | | | | | | | | | | | | | | The 32-bit defconfig version has these enabled for years so make the 64-bit defconfig have them too. This patch only adds CONFIG_VIRT_DRIVERS, CONFIG_FSL_HV_MANAGER and CONFIG_PPC_EPAPR_HV_BYTECHAN other changes being "make savedefconfig" artifacts. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl-booke: Add initial T1042RDB_PI board supportPriyanka Jain2014-09-102-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042RDB_PI is Freescale Reference Design Board supporting the T1042 QorIQ Power Architecture™ processor. T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit. The board is designed with low power features targeted for Printing Image Market. T1042RDB_PI is similar to T1040RDB board with few differences like it has video interface, supports T1042 personality only T1042RDB_PI board Overview ----------------------- - SERDES Connections, 8 lanes supporting: - PCI - SATA 2.0 - DDR Controller - Supports rates of up to 1600 MHz data-rate - Supports one DDR3LP UDIMM -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Device connected: EEPROM, thermal monitor, VID controller, RTC - Other IO - Two Serial ports - ProfiBus port Add support for T1042RDB_PI board: -add device tree -Add entry in corenet_generic.c, as it is similar to other corenet platforms Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl-booke: Add initial T1040/T1042 RDB board supportPriyanka Jain2014-09-105-1/+255
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040/T1042RDB is Freescale Reference Design Board. The board can support both T1040/T1042 QorIQ Power Architecture™ processor. T1040/T1042RDB board Overview ----------------------- - SERDES Connections, 8 lanes supporting: - PCI - SGMII - QSGMII - SATA 2.0 - DDR Controller - Supports rates of up to 1600 MHz data-rate - Supports one DDR3LP UDIMM -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Devices connected: EEPROM, thermal monitor, VID controller - Other IO - Two Serial ports - ProfiBus port Add support for T1040/T1042 RDB board: -add device tree -add entry in Kconfig to build -Add entry in corenet_generic.c, as it is similar to other corenet platforms Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Duplicate two insns instead of branchingLEROY Christophe2014-09-051-2/+4
| | | | | | | | | | | | | | | | Branching takes two cycles on MPC8xx. Lets duplicate the two instructions and avoid the branching. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Optimize verification in FixupDARLEROY Christophe2014-09-051-4/+2
| | | | | | | | | | | | | | | | By XORing the upper part of the instruction code, we get a value that can directly be verified with the second test and we can remove the first test. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: No need to save r10 and r3 when not calling FixupDARLEROY Christophe2014-09-051-14/+13
| | | | | | | | | | | | | | | | r10 and r3 are only used inside FixupDAR function. So lets save them inside that function only. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Fix comment about DIRTY updateLEROY Christophe2014-09-051-6/+2
| | | | | | | | | | | | | | | | Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not handled here anymore. So we fix the comment. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Remove loading of r10 at end of FixupDARLEROY Christophe2014-09-051-4/+3
| | | | | | | | | | | | | | | | Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore after FixupDAR. There is therefore no need to set it up with the value of DAR. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Use SCRATCH0 and SCRATCH1 also for TLB handlersLEROY Christophe2014-09-051-68/+36
| | | | | | | | | | | | | | | | | | | | SCRATCH0 and SCRATCH1 are only used in Exceptions prologs where no other exception can happen. There is therefore no need to preserve them accross TLB handlers, we can use them there as in other exceptions. One of the advantages is that they do not suffer CPU6 errata unlike M_TW register. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/8xx: Declare SPRG2 as a SCRATCH registerLEROY Christophe2014-09-052-6/+7
| | | | | | | | | | | | | | | | | | Since commit 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a scratch register just like SPRG0 and SPRG1. So Declare it as such and fix the comment which is not valid anymore since that commit. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl_msi: spread msi ints across different MSIRsTudor Laurentiu2014-09-054-11/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allocate msis such that each time a new interrupt is requested, the SRS (MSIR register select) to be used is allocated in a round-robin fashion. The end result is that the msi interrupts will be spread across distinct MSIRs with the main benefit that now users can set affinity to each msi int through the mpic irq backing up the MSIR register. This is achieved with the help of a newly introduced msi bitmap api that allows specifying the starting point when searching for a free msi interrupt. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl_msi: show more meaningful names in /proc/interruptsTudor Laurentiu2014-09-051-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename the irq controller associated with a MSI interrupt to fsl-msi-<V>, where <V> is the virq of the cascade irq backing up this MSI interrupt. This way, one can set the affinity of a MSI through the cascade irq associated with said MSI interrupt. Given this example /proc/interrupts snippet: CPU0 CPU1 CPU2 CPU3 16: 0 0 0 0 OpenPIC 16 Edge mpic-error-int 17: 0 4 0 0 fsl-msi-224 0 Edge eth0-rx-0 18: 0 5 0 0 fsl-msi-225 1 Edge eth0-tx-0 19: 0 2 0 0 fsl-msi-226 2 Edge eth0 [...] 224: 0 11 0 0 OpenPIC 224 Edge fsl-msi-cascade 225: 0 0 0 0 OpenPIC 225 Edge fsl-msi-cascade 226: 0 0 0 0 OpenPIC 226 Edge fsl-msi-cascade [...] To change the affinity of MSI interrupt 17 (having the irq controller named "fsl-msi-224") instead of writing /proc/irq/17/smp_affinity, use the associated MSI cascade irq, in this case, interrupt 224, e.g.: echo 6 > /proc/irq/224/smp_affinity Note that a MSI cascade irq covers several MSI interrupts, so changing the affinity on the cascade will impact all of the associated MSI interrupts. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl_msi: change the irq handler from chained to normalTudor Laurentiu2014-09-051-38/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we do for other fsl-mpic related cascaded irqchips (e.g. error ints, mpic timers), use a normal irq handler for msi irqs too. This brings some advantages such as mask/unmask/ack/eoi and irq state taken care behind the scenes, kstats updates a.s.o plus access to features provided by mpic, such as affinity. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl_msi: reorganize structs to improve clarity and flexibilityTudor Laurentiu2014-09-052-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Store cascade_data in an array inside the driver data for later use. Get rid of the msi_virq array since now we can encapsulate the virqs in the cascade_data directly and access them through the array mentioned earlier. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Mihai Caraman <mihai.caraman@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc: dts: t4240: Change T4240 USB controller versionNikhil Badola2014-09-041-2/+2
| | | | | | | | | | | | | | Change USB controller version to 2.5 in compatible string for T4240 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc: fsl_pci: Add forced PCI Agent enumerationAaron Sierra2014-09-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following commit prevents the MPC8548E on the XPedite5200 PrPMC module from enumerating its PCI/PCI-X bus: powerpc/fsl-pci: use 'Header Type' to identify PCIE mode The previous patch prevents any Freescale PCI-X bridge from enumerating the bus, if it is hardware strapped into Agent mode. In PCI-X, the Host is responsible for driving the PCI-X initialization pattern to devices on the bus, so that they know whether to operate in conventional PCI or PCI-X mode as well as what the bus timing will be. For a PCI-X PrPMC, the pattern is driven by the mezzanine carrier it is installed onto. Therefore, PrPMCs are PCI-X Agents, but one per system may still enumerate the bus. This patch causes the device node of any PCI/PCI-X bridge strapped into Agent mode to be checked for the fsl,pci-agent-force-enum property. If the property is present in the node, the bridge will be allowed to enumerate the bus. Cc: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Aaron Sierra <asierra@xes-inc.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc: configs: Add VFAT file-system configsNikhil Badola2014-09-045-0/+13
| | | | | | | | | | | | | | | | | | | | | | Add CONFIG_NLS_CODEPAGE_437, CONFIG_NLS_CODEPAGE_850, CONFIG_NLS_ISO8859_1 in default configs for 85xx and 86xx socs. Required for mounting vfat file-systems on USB devices Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl_msi: support vmpic msi with mpic 4.3Tudor Laurentiu2014-09-041-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | The new MSI block in MPIC 4.3 added the MSIIR1 register, with a different layout, in order to support 16 MSIR registers. The msi binding was also updated so that the "reg" reflects the newly introduced MSIIR1 register. Virtual machines advertise these msi nodes by using the compatible "fsl,vmpic-msi-v4.3" so add support for it. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/fsl-pci: Limit ZONE_DMA32 to 2GiB on 64-bit platformsScott Wood2014-09-042-0/+21
| | | | | | | | | | | | | | | | | | | | | | FSL PCI cannot directly address the whole lower 4 GiB due to conflicts with PCICSRBAR and outbound windows. By the time max_direct_dma_addr is set to the precise limit, it will be too late to alter the zone limits, but we should always have at least 2 GiB mapped (unless RAM is smaller than that). Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
| * powerpc/64: Limit ZONE_DMA32 to 4GiB in swiotlb_detect_4g()Scott Wood2014-09-041-2/+6
| | | | | | | | | | | | | | | | | | A DMA zone is still needed with swiotlb, for coherent allocations. This doesn't affect platforms that don't use swiotlb or that don't call swiotlb_detect_4g(). Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
| * powerpc/64: Honor swiotlb limit in coherent allocationsScott Wood2014-09-041-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FSL PCI cannot directly address the whole lower 4 GiB due to conflicts with PCICSRBAR and outbound windows, and thus max_direct_dma_addr is less than 4GiB. Honor that limit in dma_direct_alloc_coherent(). Note that setting the DMA mask to 31 bits is not an option, since many PCI drivers would fail if we reject 32-bit DMA in dma_supported(), and we have no control over the setting of coherent_dma_mask if dma_supported() returns true. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
| * powerpc: Dynamic DMA zone limitsScott Wood2014-09-044-5/+83
| | | | | | | | | | | | | | | | | | | | Platform code can call limit_zone_pfn() to set appropriate limits for ZONE_DMA and ZONE_DMA32, and dma_direct_alloc_coherent() will select a suitable zone based on a device's mask and the pfn limits that platform code has configured. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
* | powerpc: Enable CONFIG_CRASH_DUMP=y for ppc64_defconfigMichael Ellerman2014-10-031-0/+1
| | | | | | | | | | | | | | | | | | It pulls in more code, including causing us to build a relocatable kernel, which is good for testing. The resulting kernel is still usable as a non-crash dump kernel. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | powerpc/kdump: crash_dump.c needs to include io.hMichael Ellerman2014-10-031-0/+1
| | | | | | | | | | | | For __ioremap(). Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | powerpc: Don't build powernv for other platform defconfigsMichael Ellerman2014-10-035-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Because powernv arrived after these other platforms, the defconfigs didn't have PPC_POWERNV disabled, and being default y it gets turned on. If we're going to bother having defconfigs for the specific platforms then they should only build the code required for those platforms. The grab bag of everything config is ppc64_defconfig. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | powerpc/pci: remove duplicate declaration of pci_bus_find_capabilityWei Yang2014-10-031-1/+0
| | | | | | | | | | | | | | | | | | | | | | pci_bus_find_capability() is decleared in pci.h, so it is not necessary to do it again. This patch removes it. Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com> Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | powerpc/iommu/ddw: Fix endiannessAlexey Kardashevskiy2014-10-031-23/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rtas_call() accepts and returns values in CPU endianness. The ddw_query_response and ddw_create_response structs members are defined and treated as BE but as they are passed to rtas_call() as (u32 *) and they get byteswapped automatically, the data is CPU-endian. This fixes ddw_query_response and ddw_create_response definitions and use. of_read_number() is designed to work with device tree cells - it assumes the input is big-endian and returns data in CPU-endian. However due to the ddw_create_response struct fix, create.addr_hi/lo are already CPU-endian so do not byteswap them. ddw_avail is a pointer to the "ibm,ddw-applicable" property which contains 3 cells which are big-endian as it is a device tree. rtas_call() accepts a RTAS token in CPU-endian. This makes use of of_property_read_u32_array to byte swap and avoid the need for a number of be32_to_cpu calls. Cc: stable@vger.kernel.org # v3.13+ Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> [aik: folded Anton's patch with of_property_read_u32_array] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | powerpc: Add printk levels to powerpc codeAnton Blanchard2014-10-025-10/+10
| | | | | | | | | | | | | | Add printk levels to some places in the powerpc port. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | powerpc: Add printk levels to powernv platform codeAnton Blanchard2014-10-022-4/+4
| | | | | | | | | | | | | | | | Add printk levels to powernv platform code, and convert to pr_err() etc while here. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | powerpc: Remove powerpc specific cmd_lineAnton Blanchard2014-10-028-16/+10
| | | | | | | | | | | | | | | | There is no need for yet another copy of the command line, just use boot_command_line like everyone else. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | powerpc: Use pr_fmt in module loader codeAnton Blanchard2014-10-022-36/+31
| | | | | | | | | | | | | | | | | | | | Use pr_fmt to give some context to the error messages in the module code, and convert open coded debug printk to pr_debug. Use pr_err for error messages. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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