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* ARM: mxs: add initial pm supportShawn Guo2011-01-262-0/+44
| | | | | | | | | This is a very initial pm support and basically does nothing. With this pm support entry, drivers can start testing their own pm functions. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM MXS: Add auart platform support for i.MX28Sascha Hauer2011-01-256-0/+81
| | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx: Add initial support for IMX27IPCAM boardFabio Estevam2011-01-254-0/+88
| | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mx5/mx51_3ds: Add watchdog supportDaiane Angolini2011-01-242-0/+2
| | | | | Signed-off-by: Daiane Angolini <daiane.angolini@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mxs/mx28evk: read fec mac address from ocotpShawn Guo2011-01-211-1/+34
| | | | | | | | Read fec mac address from ocotp and save it into fec_platform_data mac field for fec driver to use. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mxs: add ocotp read functionShawn Guo2011-01-214-0/+97
| | | | | Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mx5: Use dummy clock for the keypadFabio Estevam2011-01-211-5/+1
| | | | | | | Reuse dummy_clk for the imx-keypad device instead of using a dedicated kpp_clk. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: i.MX53: Add full iomux support for mx53Dinh Nguyen2011-01-212-311/+2361
| | | | | | | | This iomux file contains all the available pins that are iomux capable. Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Introduce VPR200 board.Marc Reilly2011-01-193-0/+342
| | | | | Signed-off-by: Marc Reilly <marc@cpdesign.com.au> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: mx50_rdp: add i2c bus supportRichard Zhao2011-01-193-0/+20
| | | | | Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* arm: mx50_rdp: add fec supportRichard Zhao2011-01-194-2/+31
| | | | | Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX50: Rename devices-mx50.hJason Liu2011-01-192-1/+1
| | | | | | | | | | | There are devices-imx51.h and devices-imx53.h under arch/arm/mach-mx5 directory. So, had better rename devices-mx50.h to devices-imx50.h to follow the same naming convention with imx51 and imx53 part. Signed-off-by: Jason Liu <r64343@freescale.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblazeLinus Torvalds2011-01-182-2/+5
|\ | | | | | | | | | | * 'next' of git://git.monstr.eu/linux-2.6-microblaze: microblaze: Fix asm/pgtable.h microblaze: Fix missing pagemap.h
| * microblaze: Fix asm/pgtable.hMichal Simek2011-01-161-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function ptep_test_and_clear_young have had wrong the first argument. It is also necessary to add __HAVE macros for ptep_test_and_clear_young and ptep_get_and_clear functions. Error log: In file included from linux/arch/microblaze/include/asm/pgtable.h:570, from arch/microblaze/mm/pgtable.c:35: include/asm-generic/pgtable.h:23: error: conflicting types for 'ptep_test_and_clear_young' linux/arch/microblaze/include/asm/pgtable.h:449: error: previous definition of 'ptep_test_and_clear_young' was here include/asm-generic/pgtable.h:73: error: redefinition of 'ptep_get_and_clear' linux/arch/microblaze/include/asm/pgtable.h:462: error: previous definition of 'ptep_get_and_clear' was here Signed-off-by: Michal Simek <monstr@monstr.eu>
| * microblaze: Fix missing pagemap.hMichal Simek2011-01-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing linux/pagemap.h to solve compilation error. Error log: In file included from linux/arch/microblaze/include/asm/tlb.h:17, from mm/pgtable-generic.c:9: include/asm-generic/tlb.h: In function 'tlb_flush_mmu': include/asm-generic/tlb.h:76: error: implicit declaration of function 'release_pages' include/asm-generic/tlb.h: In function 'tlb_remove_page': include/asm-generic/tlb.h:105: error: implicit declaration of function 'page_cache_release' Signed-off-by: Michal Simek <monstr@monstr.eu>
* | Merge branch 'for-linus' of ↵Linus Torvalds2011-01-1838-623/+727
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (25 commits) m68knommu: fix broken setting of irq_chip and handler m68knommu: switch to using -mcpu= flags for ColdFire targets m68knommu: arch/m68knommu/Kconfig whitespace cleanup m68knommu: create optimal separate instruction and data cache for ColdFire m68knommu: support ColdFire caches that do copyback and write-through m68knommu: support version 2 ColdFire split cache m68knommu: make cache push code ColdFire generic m68knommu: clean up ColdFire cache control code m68knommu: move inclusion of ColdFire v4 cache registers m68knommu: merge bit definitions for version 3 ColdFire cache controller m68knommu: create bit definitions for the version 2 ColdFire cache controller m68knommu: remove empty __iounmap() it is no used m68knommu: remove kernel_map() code, it is not used m68knommu: remove do_page_fault(), it is not used m68knommu: use user stack pointer hardware on some ColdFire cores m68knommu: remove command line printing DEBUG m68knommu: remove fasthandler interrupt code m68knommu: move UART addressing to part specific includes m68knommu: fix clock rate value reported for ColdFire 54xx parts m68knommu: move ColdFire CPU names into their headers ...
| * | m68knommu: fix broken setting of irq_chip and handlerGreg Ungerer2011-01-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix compile error, by using correct loop variable: arch/m68knommu/platform/68328/ints.c: In function ‘init_IRQ’: arch/m68knommu/platform/68328/ints.c:182: error: ‘irq’ undeclared (first use in this function) arch/m68knommu/platform/68328/ints.c:182: error: (Each undeclared identifier is reported only once arch/m68knommu/platform/68328/ints.c:182: error: for each function it appears in.) Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: switch to using -mcpu= flags for ColdFire targetsGreg Ungerer2011-01-051-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Gcc has deprecated the use of the following ColdFire cpu options: -m5206e, -m528x, -m5307 and -m5407. In there place we should use the equivilent -mcpu= option and setting. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: arch/m68knommu/Kconfig whitespace cleanupPhilippe De Muyter2011-01-051-10/+10
| | | | | | | | | | | | | | | | | | | | | Replace 8 spaces, or even 7, by TAB at begin of lines. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: create optimal separate instruction and data cache for ColdFireGreg Ungerer2011-01-054-20/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create separate functions to deal with instruction and data cache flushing. This way we can optimize them for the vairous cache types and arrangements used across the ColdFire family. For example the unified caches in the version 3 cores means we don't need to flush the instruction cache. For the version 2 cores that do not do data cacheing (or where we choose instruction cache only) we don't need to do any data flushing. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: support ColdFire caches that do copyback and write-throughGreg Ungerer2011-01-053-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | The version 3 and version 4 ColdFire cache controllers support both write-through and copy-back modes on the data cache. Allow for Kconfig time configuration of this, and set the cache mode appropriately. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: support version 2 ColdFire split cacheGreg Ungerer2011-01-052-14/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newer version 2 ColdFire CPU cores support a configurable cache arrangement. The cache memory can be used as all instruction cache, all data cache, or split in half for both instruction and data caching. Support this setup via a Kconfig time menu that allows a kernel builder to choose the arrangement they want to use. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: make cache push code ColdFire genericGreg Ungerer2011-01-054-39/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the code to push cache lines is only available to version 4 cores. Version 3 cores may also need to use this if we support copy- back caches on them. Move this code to make it more generic, and useful for all version ColdFire cores. With this in place we can now have a single cache_flush_all() code path that does all the right things on all version cores. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: clean up ColdFire cache control codeGreg Ungerer2011-01-056-192/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cache control code for the ColdFire CPU's is a big ugly mess of "#ifdef"ery liberally coated with bit constants. Clean it up. The cache controllers in the various ColdFire parts are actually quite similar. Just differing in some bit flags and options supported. Using the header defines now in place it is pretty easy to factor out the small differences and use common setup and flush/invalidate code. I have preserved the cache setups as they where in the old code (except where obviously wrong - like in the case of the 5249). Following from this it should be easy now to extend the possible setups used on the CACHE controllers that support split cacheing or copy-back or write through options. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: move inclusion of ColdFire v4 cache registersGreg Ungerer2011-01-054-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the inclusion of the version 4 cache controller registers so that it is with all the other register bit flag definitions. This makes it consistent with the other version core inclusion points, and means we don't need "#ifdef"ery in odd-ball places for these definitions. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: merge bit definitions for version 3 ColdFire cache controllerGreg Ungerer2011-01-053-54/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | All version 3 based ColdFire CPU cores have a similar cache controller. Merge all the exitsing definitions into a single file, and make them similar in style and naming to the existing version 2 and version 4 cache controller definitions. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: create bit definitions for the version 2 ColdFire cache controllerGreg Ungerer2011-01-058-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: remove empty __iounmap() it is no usedGreg Ungerer2011-01-052-10/+0
| | | | | | | | | | | | | | | | | | The empty __iounmap() function is not used on m68knommu at all. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: remove kernel_map() code, it is not usedGreg Ungerer2011-01-052-34/+1
| | | | | | | | | | | | | | | | | | The kernel_map() functions is not used anywhere, remove it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: remove do_page_fault(), it is not usedGreg Ungerer2011-01-052-58/+1
| | | | | | | | | | | | | | | | | | The non-MMU m68k does not use the do_page_fault() code, so remove it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: use user stack pointer hardware on some ColdFire coresGreg Ungerer2011-01-057-55/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | The more modern ColdFire parts (even if based on older version cores) have separate user and supervisor stack pointers (a7 register). Modify the ColdFire CPU setup and exception code to enable and use this on parts that have it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: remove command line printing DEBUGGreg Ungerer2011-01-051-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | There is no need for the DEBUG based command line printing in here. The kernel will print out the command line in the banner later in the boot up. So remove it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: remove fasthandler interrupt codeGreg Ungerer2011-01-051-27/+1
| | | | | | | | | | | | | | | | | | | | | There are no users of the old "fasthandler" interrupt entry code. So remove it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: move UART addressing to part specific includesGreg Ungerer2011-01-0512-45/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ColdFire UART base addresses varies between the different ColdFire family members. Instead of keeping the base addresses with the UART definitions keep them with the other addresses definitions for each ColdFire part. The motivation for this move is so that when we add new ColdFire part definitions, they are all in a single file (and we shouldn't normally need to modify the UART definitions in mcfuart.h at all). Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: fix clock rate value reported for ColdFire 54xx partsGreg Ungerer2011-01-0512-21/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The instruction timings of the ColdFire 54xx family parts are different to other version 4 parts (or version 2 or 3 parts for that matter too). Move the instruction timing setting into the ColdFire part specific headers, and set the 54xx value appropriately. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: move ColdFire CPU names into their headersGreg Ungerer2011-01-0512-44/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the ColdFire CPU names out of setup.c and into their repsective headers. That way when we add new ones we won't need to modify setup.c any more. Add the missing 548x CPU name. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: add support for the ColdFire 547x family of processorsGreg Ungerer2011-01-051-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | The Freescale M547x family of ColdFire processors is very similar to the M548x series. We use all the same support for it. Initially all we need is a high level configuration option for it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: make Coldfire 548x support more genericGreg Ungerer2011-01-0514-44/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ColdFire 547x family of processors is very similar to the ColdFire 548x series. Almost all of the support for them is the same. Make the code supporting the 548x more gneric, so it will be capable of supporting both families. For the most part this is a renaming excerise to make the support code more obviously apply to both families. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: Use symbolic constants for cache operations on M54xxPhilippe De Muyter2011-01-053-17/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have meaningfull symbolic constants for bit definitions of the cache registers of m5407 and m548x chips, use them to improve readability, portability and efficiency of the cache operations. This also fixes __flush_cache_all for m548x chips : implicit DCACHE_SIZE was exact for m5407, but wrong for m548x. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: Move __flush_cache_all definition for m54xx in m54xxacr.hPhilippe De Muyter2011-01-052-23/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | __flush_cache_all for m54xx is intrinsically related to the bit definitions in m54xxacr.h. Move it there from cacheflush_no.h, for easier maintenance. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
| * | m68knommu: Create new m54xxacr.h from m5407sim.h subpartPhilippe De Muyter2011-01-052-34/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MCF548x have the same cache control registers as the MCF5407. Extract the bit definitions for the ACR and CACR registers from m5407sim.h and move them to a new file m54xxacr.h. Those definitions are not used anywhere yet, so no other file is involved. This is a preparation for m54xx cache support cleanup. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
* | | Merge branch 'perf-fixes-for-linus' of ↵Linus Torvalds2011-01-181-0/+1
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: perf tools: Fix tracepoint id to string perf.data header table perf tools: Fix handling of wildcards in tracepoint event selectors powerpc: perf: Fix frequency calculation for overflowing counters
| * | | powerpc: perf: Fix frequency calculation for overflowing countersAnton Blanchard2011-01-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When profiling a benchmark that is almost 100% userspace, I noticed some wildly inaccurate profiles that showed almost all time spent in the kernel. Closer examination shows we were programming a tiny number of cycles into the PMU after each overflow (about ~200 away from the next overflow). This gets us stuck in a loop which we eventually break out of by throttling the PMU (there are regular throttle/unthrottle events in the log). It looks like we aren't setting event->hw.last_period to something same and the frequency to period calculations in perf are going haywire. With the following patch we find the correct period after a few interrupts and stay there. I also see no more throttle events. Signed-off-by: Anton Blanchard <anton@samba.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linuxppc-dev@lists.ozlabs.org Cc: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> LKML-Reference: <20110117161742.5feb3761@kryten> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | | ARM: S5PV310: Add missing virtual ASoC DMA deviceJassi Brar2011-01-182-2/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | | ARM: S5PV210: Add missing virtual ASoC DMA deviceJassi Brar2011-01-182-0/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | | ARM: S5P6450: Add missing virtual ASoC DMA deviceJassi Brar2011-01-181-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | | ARM: S5P6440: Add missing virtual ASoC DMA deviceJassi Brar2011-01-181-0/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | | ARM: S5P6442: Enable I2S device to work on SMDK6442Jassi Brar2011-01-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing virtual ASoC DMA device. Signed-off-by: Jassi Brar <jassi.brar@samsung.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> [kgene.kim@samsung.com: minor changed title] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | | | Merge branch 'next-devicetree' of git://git.secretlab.ca/git/linux-2.6Linus Torvalds2011-01-173-8/+6
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * 'next-devicetree' of git://git.secretlab.ca/git/linux-2.6: spi/spi_sh_msiof: fix a wrong free_irq() parameter dt/flattree: Return virtual address from early_init_dt_alloc_memory_arch()
| * | | | dt/flattree: Return virtual address from early_init_dt_alloc_memory_arch()Grant Likely2011-01-163-8/+6
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | The physical address is never used by the device tree code when allocating memory for unflattening. Change the architecture's alloc hook to return the virutal address instead. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 23:49:26 +0100