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* arm64: Add initial DTS for APM X-Gene Storm SOC and APM Mustang boardVinayak Kale2013-06-203-0/+143
| | | | | | | | | This patch adds initial DTS files required for APM Mustang board. Signed-off-by: Kumar Sankaran <ksankaran@apm.com> Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Add defines for APM ARMv8 implementationVinayak Kale2013-06-201-0/+3
| | | | | | | | | This patch adds defines for APM CPU implementer ID and APM CPU part numbers in asm/cputype.h Signed-off-by: Kumar Sankaran <ksankaran@apm.com> Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Enable APM X-Gene SOC family in the defconfigVinayak Kale2013-06-201-0/+4
| | | | | | | | | This patch enables APM X-Gene SOC family in the defconfig. It also enables 8250 serial driver needed by X-Gene SOC family. Signed-off-by: Kumar Sankaran <ksankaran@apm.com> Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64: Add Kconfig option for APM X-Gene SOC familyVinayak Kale2013-06-201-0/+7
| | | | | | | | | This patch adds arm64/Kconfig option for APM X-Gene SOC family. Signed-off-by: Kumar Sankaran <ksankaran@apm.com> Signed-off-by: Loc Ho <lho@apm.com> Signed-off-by: Feng Kan <fkan@apm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* arm64/Makefile: provide vdso_install targetKyle McMartin2013-06-191-0/+4
| | | | | | | | | Provide a vdso_install target in the arm64 Makefile, as other architectures with a vdso do. Signed-off-by: Kyle McMartin <kyle@redhat.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* Merge branch 'kvm-arm64/kvm-for-3.11' of ↵Catalin Marinas2013-06-1228-1/+4539
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into upstream * 'kvm-arm64/kvm-for-3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms: (33 commits) arm64: KVM: document kernel object mappings in HYP arm64: KVM: MAINTAINERS update arm64: KVM: userspace API documentation arm64: KVM: enable initialization of a 32bit vcpu arm64: KVM: 32bit guest fault injection arm64: KVM: 32bit specific register world switch arm64: KVM: CPU specific 32bit coprocessor access arm64: KVM: 32bit handling of coprocessor traps arm64: KVM: 32bit conditional execution emulation arm64: KVM: 32bit GP register access arm64: KVM: define 32bit specific registers arm64: KVM: Build system integration arm64: KVM: PSCI implementation arm64: KVM: Plug the arch timer ARM: KVM: timer: allow DT matching for ARMv8 cores arm64: KVM: Plug the VGIC arm64: KVM: Exit handling arm64: KVM: HYP mode world switch implementation arm64: KVM: hypervisor initialization code arm64: KVM: guest one-reg interface ... Conflicts: arch/arm64/Makefile
| * arm64: KVM: enable initialization of a 32bit vcpuMarc Zyngier2013-06-124-2/+33
| | | | | | | | | | | | | | | | | | | | | | | | Wire the init of a 32bit vcpu by allowing 32bit modes in pstate, and providing sensible defaults out of reset state. This feature is of course conditioned by the presence of 32bit capability on the physical CPU, and is checked by the KVM_CAP_ARM_EL1_32BIT capability. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: 32bit guest fault injectionMarc Zyngier2013-06-121-1/+78
| | | | | | | | | | | | | | | | Add fault injection capability for 32bit guests. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: 32bit specific register world switchMarc Zyngier2013-06-121-0/+70
| | | | | | | | | | | | | | | | | | Allow registers specific to 32bit guests to be saved/restored during the world switch. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: CPU specific 32bit coprocessor accessMarc Zyngier2013-06-121-0/+10
| | | | | | | | | | | | | | | | | | Enable handling of CPU specific 32bit coprocessor access. Not much here either. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: 32bit handling of coprocessor trapsMarc Zyngier2013-06-123-7/+186
| | | | | | | | | | | | | | | | | | | | | | Provide the necessary infrastructure to trap coprocessor accesses that occur when running 32bit guests. Also wire SMC and HVC trapped in 32bit mode while were at it. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: 32bit conditional execution emulationMarc Zyngier2013-06-123-3/+170
| | | | | | | | | | | | | | | | | | As conditional instructions can trap on AArch32, add the thinest possible emulation layer to keep 32bit guests happy. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: 32bit GP register accessMarc Zyngier2013-06-123-2/+183
| | | | | | | | | | | | | | | | Allow access to the 32bit register file through the usual API. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: define 32bit specific registersMarc Zyngier2013-06-123-3/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Define the 32bit specific registers (SPSRs, cp15...). Most CPU registers are directly mapped to a 64bit register (r0->x0...). Only the SPSRs have separate registers. cp15 registers are also mapped into their 64bit counterpart in most cases. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: Build system integrationMarc Zyngier2013-06-122-0/+24
| | | | | | | | | | | | | | | | Only the Makefile is plugged in. The Kconfig stuff is in a separate patch to allow for an easier merge process. Reviewed-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: PSCI implementationMarc Zyngier2013-06-124-10/+47
| | | | | | | | | | | | | | | | Wire the PSCI backend into the exit handling code. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: Plug the arch timerMarc Zyngier2013-06-122-0/+68
| | | | | | | | | | | | | | | | Add support for the in-kernel timer emulation. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * ARM: KVM: timer: allow DT matching for ARMv8 coresMarc Zyngier2013-06-121-0/+1
| | | | | | | | | | | | | | ARMv8 cores have the exact same timer as ARMv7 cores. Make sure the KVM timer code can match it in the device tree. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: Plug the VGICMarc Zyngier2013-06-121-0/+88
| | | | | | | | | | | | | | | | Add support for the in-kernel GIC emulation. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: Exit handlingMarc Zyngier2013-06-121-0/+119
| | | | | | | | | | | | | | | | | | Handle the exit of a VM, decoding the exit reason from HYP mode and calling the corresponding handler. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: HYP mode world switch implementationMarc Zyngier2013-06-122-0/+650
| | | | | | | | | | | | | | | | | | | | The HYP mode world switch in all its glory. Implements save/restore of host/guest registers, EL2 trapping, IPA resolution, and additional services (tlb invalidation). Reviewed-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: hypervisor initialization codeMarc Zyngier2013-06-072-0/+120
| | | | | | | | | | | | | | Provide EL2 with page tables and stack, and set the vectors to point to the full blown world-switch code. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: guest one-reg interfaceMarc Zyngier2013-06-071-0/+259
| | | | | | | | | | | | | | Let userspace play with the guest registers. Reviewed-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: MMIO access backendMarc Zyngier2013-06-071-0/+59
| | | | | | | | | | | | | | | | Define the necessary structures to perform an MMIO access. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: kvm_arch and kvm_vcpu_arch definitionsMarc Zyngier2013-06-071-0/+186
| | | | | | | | | | | | | | | | | | Provide the architecture dependent structures for VM and vcpu abstractions. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: virtual CPU resetMarc Zyngier2013-06-071-0/+76
| | | | | | | | | | | | | | | | Provide the reset code for a virtual CPU booted in 64bit mode. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: CPU specific system registers handlingMarc Zyngier2013-06-071-0/+85
| | | | | | | | | | | | | | | | | | Add the support code for CPU specific system registers. Not much here yet. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: system register handlingMarc Zyngier2013-06-074-0/+1101
| | | | | | | | | | | | | | | | | | Provide 64bit system register handling, modeled after the cp15 handling for ARM. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: user space interfaceMarc Zyngier2013-06-071-0/+117
| | | | | | | | | | | | | | | | | | Provide the kvm.h file that defines the user space visible interface. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: architecture specific MMU backendMarc Zyngier2013-06-071-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | Define the arm64 specific MMU backend: - HYP/kernel VA offset - S2 4/64kB definitions - S2 page table populating and flushing - icache cleaning Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: fault injection into a guestMarc Zyngier2013-06-071-0/+126
| | | | | | | | | | | | | | | | | | Implement the injection of a fault (undefined, data abort or prefetch abort) into a 64bit guest. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: Basic ESR_EL2 helpers and vcpu register accessMarc Zyngier2013-06-071-0/+158
| | | | | | | | | | | | | | | | | | Implements helpers for dealing with the EL2 syndrome register as well as accessing the vcpu registers. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: system register definitions for 64bit guestsMarc Zyngier2013-06-071-0/+68
| | | | | | | | | | | | | | | | Define the saved/restored registers for 64bit guests. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: EL2 register definitionsMarc Zyngier2013-06-071-0/+245
| | | | | | | | | | | | | | | | Define all the useful bitfields for EL2 registers. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: HYP mode idmap supportMarc Zyngier2013-06-071-0/+20
| | | | | | | | | | | | | | | | | | | | | | Add the necessary infrastructure for identity-mapped HYP page tables. Idmap-ed code must be in the ".hyp.idmap.text" linker section. The rest of the HYP ends up in ".hyp.text". Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| * arm64: KVM: define HYP and Stage-2 translation page flagsMarc Zyngier2013-06-073-0/+37
| | | | | | | | | | | | | | | | Add HYP and S2 page flags, for both normal and device memory. Reviewed-by: Christopher Covington <cov@codeaurora.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | Merge tag 'xen-arm64-3.1-tag' of ↵Catalin Marinas2013-06-1213-2/+165
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen into upstream Introduce Xen support to ARM64 * tag 'xen-arm64-3.1-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/sstabellini/xen: MAINTAINERS: add myself as arm64/xen maintainer arm64/xen: introduce CONFIG_XEN and hypercall.S on ARM64 arm64/xen: use XEN_IO_PROTO_ABI_ARM on ARM64 arm64/xen: implement ioremap_cached on arm64 arm64/xen: introduce asm/xen header files on arm64 arm/xen: define xen_remap as ioremap_cached
| * | arm64/xen: introduce CONFIG_XEN and hypercall.S on ARM64Stefano Stabellini2013-06-074-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce CONFIG_XEN and the implementation of hypercall.S (that is the only ARMv8 specific code in Xen support for ARM). Compile enlighten.c and grant_table.c from arch/arm. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
| * | arm64/xen: implement ioremap_cached on arm64Stefano Stabellini2013-06-071-0/+2
| | | | | | | | | | | | Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
| * | arm64/xen: introduce asm/xen header files on arm64Stefano Stabellini2013-06-077-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | asm/xen/hypercall.h, asm/xen/hypervisor.h, asm/xen/interface.h and asm/xen/page.h are identical so to avoid code duplication we are just including the original arm header files here. asm/xen/events.h is slightly different, so introduce a different file here (use xchg to implement xchg_xen_ulong and pass regs->pstate to raw_irqs_disabled_flags). Also introduce asm/hypervisor.h and asm/sync_bitops.h. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Acked-by: Ian Campbell <ian.campbell@citrix.com>
| * | arm/xen: define xen_remap as ioremap_cachedStefano Stabellini2013-06-041-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define xen_remap as ioremap_cache (MT_MEMORY and MT_DEVICE_CACHED end up having the same AttrIndx encoding). Remove include asm/mach/map.h, not unneeded. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
* | | arm64: debug: consolidate software breakpoint handlersWill Deacon2013-06-125-66/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The software breakpoint handlers are hooked in directly from ptrace, which makes it difficult to add additional handlers for things like kprobes and kgdb. This patch moves the handling code into debug-monitors.c, where we can dispatch to different debug subsystems more easily. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | | arm64: extable: sort the exception table at build timeWill Deacon2013-06-122-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As is done for other architectures, sort the exception table at build-time rather than during boot. Since sortextable appears to be a standalone C program relying on the host elf.h to provide EM_AARCH64, I've had to add a conditional check in order to allow cross-compilation on machines that aren't running a bleeding-edge libc-dev. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | | arm64: device: add iommu pointer to device archdataWill Deacon2013-06-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using an IOMMU for device mappings, it is necessary to keep a pointer between the device and the IOMMU to which it is attached in order to obtain the correct IOMMU when attaching the device to a domain. This patch adds an iommu pointer to the dev_archdata structure, in a similar manner to other architectures (ARM, PowerPC, x86, ...). Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | | arm64: pgtable: use pte_index instead of __pte_indexWill Deacon2013-06-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | pte_index is a useful helper outside of arch/arm64, for things like the ARM SMMU driver, so rename __pte_index to pte_index to be consistent with both arch/arm/ and also the definitions of pmd_index and pgd_index. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | | arm64: kernel: compiling issue, need delete read_current_timer()Chen Gang2013-06-102-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Under arm64, we will calibrate the delay loop statically using a known timer frequency, so delete read_current_timer(), or it will cause compiling issue with allmodconfig. The related error: ERROR: "read_current_timer" [lib/rbtree_test.ko] undefined! ERROR: "read_current_timer" [lib/interval_tree_test.ko] undefined! ERROR: "read_current_timer" [fs/ext4/ext4.ko] undefined! ERROR: "read_current_timer" [crypto/tcrypt.ko] undefined! Signed-off-by: Chen Gang <gang.chen@asianux.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | | arm64: mm: don't bother invalidating the icache in switch_mmWill Deacon2013-06-071-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | We don't support software broadcast of cache maintenance operations, so this flush is not required (__sync_icache_dcache will always affect all CPUs). Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | | arm64: spinlock: retry trylock operation if strex fails on free lockCatalin Marinas2013-06-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An exclusive store instruction may fail for reasons other than lock contention (e.g. a cache eviction during the critical section) so, in line with other architectures using similar exclusive instructions (alpha, mips, powerpc), retry the trylock operation if the lock appears to be free but the strex reported failure. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Tony Thompson <anthony.thompson@arm.com> Acked-by: Will Deacon <will.deacon@arm.com>
* | | arm64: Remove __flush_dcache_page()Catalin Marinas2013-06-073-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is only used in __sync_icache_dcache(), so remove it and call __flush_dcache_area() directly. The flush_icache_user_range() function is not used in the arm64 kernel. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Will Deacon <will.deacon@arm.com> Acked-by: Will Deacon <will.deacon@arm.com>
* | | arm64: Do not flush the D-cache for anonymous pagesCatalin Marinas2013-06-072-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The D-cache on AArch64 is VIPT non-aliasing, so there is no need to flush it for anonymous pages. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Will Deacon <will.deacon@arm.com> Acked-by: Will Deacon <will.deacon@arm.com>
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