| Commit message (Collapse) | Author | Age | Files | Lines |
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
Pull "second round of Rockchip dts32 changes for 4.14" from Heiko Stübner:
A lot of attention for the rv1108 soc targetted at media-processing
(usb, operating points, spi, pwm, adc, watchdog, i2c and devices for
its evb).
RK3228/3229 gets iommu and spi nodes. Similar to the rk3288 which
also gets some more iommu nodes as well as getting converted to 64
bit addresses due to wanting to address more than 4GB of memory
via LPAE.
* tag 'v4.14-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: enable usb for rv1108-evb
ARM: dts: rockchip: add usb nodes for rv1108 SoCs
dt-bindings: update grf-binding for rv1108 SoCs
ARM: dts: rockchip: add cpu power supply for rv1108 evb
ARM: dts: rockchip: add cpu opp table for rv1108
ARM: dts: rockchip: add rk322x iommu nodes
ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb
ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb
ARM: dts: rockchip: add pwm backlight for rv1108 evb
ARM: dts: rockchip: add pwm dt nodes for rv1108
ARM: dts: rockchip: add spi dt node for rv1108
ARM: dts: rockchip: add saradc support for rv1108
ARM: dts: rockchip: add watchdog dt node for rv1108
ARM: dts: rockchip: add i2c dt nodes for rv1108
clk: rockchip: fix up indentation of some RV1108 clock-ids
clk: rockchip: rename the clk id for HCLK_I2S1_2CH
clk: rockchip: add more clk ids for rv1108
ARM: dts: rockchip: add more iommu nodes on rk3288
ARM: dts: rockchip: convert rk3288 device tree files to 64 bits
ARM: dts: rockchip: add spi node and spi pinctrl on rk3228/rk3229
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Rockchip's rv1108-evb board has one usb otg controller and one usb
host controller, each usb controller connect with one usb-phy port
through UTMI+ interface. This patch enables them to support usb on
rv1108-evb board.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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This patch adds usb otg/host controllers and phys nodes for RV1108 SoCs.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The cpu is powered by regulator vdd_core on RV1108 evalution
board. Add it to the cpu dt node.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add cpu opp table for rv1108 to support frequency
from 408MHZ to 1008MHZ.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add VPU/VDEC/VOP/IEP iommu nodes
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add dt node of bosch accelerometer bma250e on rv1108 evb.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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RK805 is used as the voltage regulator on rv1108 evaluation
board. Add device tree node for it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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RV1108 EVB uses pwm0 modulate the backlight, add dt
node to enable it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add pwm device tree node for rv1108 soc
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add SPI device tree node for rv1108.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add saradc device tree node for rv1108 soc
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add watchdog device tree node for rv1108
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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There are four i2c controllers on rv1108, add
device tree node for them.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add IEP/ISP/VPU/HEVC iommu nodes
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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In order to be able to use more than 4GB of RAM when the LPAE is
activated, the dts must be converted in 64 bits.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add spi node and spi pinctrl for rk322x
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into next/dt
Pull "Aspeed devicetree updates for 4.14" from Joel Stanley:
- fix to expose the full flash windows on ast2400.
* tag 'aspeed-4.14-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed:
ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers
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The window of the Aspeed AST2400 SMC Controllers to map chips on the
AHB Bus has a 256MB size. The full window range is
[ 0x20000000 - 0x2FFFFFFF ] for the FMC controller
[ 0x30000000 - 0x3FFFFFFF ] for the SPI controller
This change requires CONFIG_VMSPLIT_2G to be set.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Pull "Samsung DTS ARM changes for v4.14, part 2" from Krzysztof Kozłowski:
Fix PCI bus dtc warnings.
* tag 'samsung-dt-4.14-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: fix PCI bus dtc warnings
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dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/dt
Pull "Add device-tree node for display on Lego Mindstorms EV3" from Sekhar Nori:
* tag 'davinci-for-v4.14/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: dts: da850-lego-ev3: Add node for LCD display
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This adds a new node for the LEGO MINDSTORMS EV3 LCD display.
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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next/dt
Pull "arm: Xilinx Zynq DT fixes for v4.14" from Michal Simek:
- Remove earlycon
- Use C pre-processor
- Add fpga full region
- Add ethernet-phy as device-type
- Add adv7511 nodes to zc70x
* tag 'zynq-dt-for-4.14' of https://github.com/Xilinx/linux-xlnx:
arm: zynq: Remove earlycon from bootargs
arm: zynq: Use C pre-processor for includes in dts
arm: zynq: Label whole PL part as fpga_full region
arm: zynq: Add device-type property for zynq ethernet phy nodes
arm: zynq: Add adv7511 on i2c bus for zc70x
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Earlyconsole is used for early kernel debugging that's why this option
shouldn't be enabled by default.
Earlyconsole is partially copying the part of the bootlog after
"bootconsole [uart0] disabled".
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Change the dtsi include code to use the C pre-processor #include instead
of the device tree /include/. This brings all Zynq device trees inline
with each other.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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This will simplify dt overlay structure for the whole PL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Mention device-type = "ethernet-phy", as qemu will need this in absence
of compatible.
Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Describe adv7511 on i2c bus.
Signed-off-by: Christian Kohn <christian.kohn@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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This adds the operating points to the Ux500 device tree and
deletes the old special-purpose cpufreq node, as we can now
use the generic DT cpufreq driver.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Pull "Allwinner device tree changes for 4.14, round 2" from Chen-Yu Tsai:
The usual improvements:
- AXP813/AXP818 PMIC (mfd and codec) enabled for Allwinner A83T boards
- USB enabled for Allwinner A83T boards
* tag 'sunxi-dt-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: sun8i: a83t: h8homlet-v2: Enable USB ports
ARM: sun8i: a83t: cubietruck-plus: Enable onboard USB peripherals
ARM: sun8i: a83t: Add device node for USB OTG controller
ARM: sun8i: a83t: Add USB PHY and host device nodes
ARM: sun8i: a83t: h8homlet-v2: Enable AC100 combo chip in AXP818 PMIC
ARM: sun8i: a83t: h8homlet-v2: Enable PMIC part of AXP818 PMIC
ARM: sun8i: a83t: cubietruck-plus: Enable AC100 combo chip in AXP818 PMIC
ARM: sun8i: a83t: cubietruck-plus: Enable PMIC part of AXP818 PMIC
ARM: sun8i: a83t: Add device node and pinmux setting for RSB controller
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The h8homlet board has the A83T's standard USB 1.1/2.0 host pair routed
to a USB host port on the board. The other USB host port is routed to
USB OTG controller.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The Cubietruck-plus has a GL830 USB-to-SATA bridge connected to EHCI0,
and a USB3503 HSIC USB 2.0 hub connected to EHCI1. The USB3503's I2C
control interface is not connected.
This patch enables both EHCI controllers, adds a device node for the
USB hub, and includes sunxi-common-regulators.dtsi for the VBUS
regulators. The existing reg_vcc3v3 is dropped as it is also available
in the set of common regulators. Other unused regulators are disabled.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The USB OTG controller found on the A83T is compatible with the one
found on the A33.
Add a device node for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The A83T has 3 USB PHYs, 1 for USB OTG, 1 for standard USB 2.0, 1 for
USB HSIC. EHCI0/OHCI0 are the standard USB host pair, while EHCI1 is
the host controller for HSIC. OTG is not added yet.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies
in one package sharing the serial bus (I2C/RSB) pins. One die is the
actual PMIC. The other is an AC100 codec / RTC combo chip.
This patch adds the device nodes for the AC100 chip to the h8homlet-v2
device tree.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies
in one package sharing the serial bus (I2C/RSB) pins. One die is the
actual PMIC. The other is an AC100 codec / RTC combo chip.
This patch enables the RSB controller and adds a device node for the
PMIC die to the h8homlet-v2 device tree. Since the AXP813 and AXP818
are virtually identical, this patch uses the compatible string for
the former as a fallback.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies
in one package sharing the serial bus (I2C/RSB) pins. One die is the
actual PMIC. The other is an AC100 codec / RTC combo chip.
This patch adds the device nodes for the AC100 chip to the Cubietruck
Plus device tree.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies
in one package sharing the serial bus (I2C/RSB) pins. One die is the
actual PMIC. The other is an AC100 codec / RTC combo chip.
This patch enables the RSB controller and adds a device node for the
PMIC die to the Cubietruck Plus device tree. Since the AXP813 and
AXP818 are virtually identical, this patch uses the compatible string
for the former as a fallback.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The A83T has an RSB controller for talking to the PMIC and audio codec.
Add a device node for it. Since there is only one usable pinmux setting,
for it, add that as well.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Pull "Second Round of Renesas ARM Based SoC DT Updates for v4.14" from Simon Horman:
* Use newly added Gen-3 fallback compat string
This is consistent with ongoing efforts to use per-generation
fallback strings where appropriate across devices found
on R-Car SoCs. The aim of the effort being to strike a balance
between the limited information available about the compatibility
of devices found on different SoCs and the desire to ease enabling
devices on new SoCs.
This has no run-time effect due to the presence of a per-SoC
compat string.
* Enable second CPU core on RZ/G1M (r8a7743)
The RZ/G1M has two CA15 cores running at up to 1.5GHz
* Enable frequency scaling on RZ/G1M (r8a7743)
* Add six I2C cores to RZ/G1M (r8a7743) SoC DT
This is a step towards enabling these cores on boards that use this SoC
* Add CEC clock for HDMI transmitter to R-Car M2-W (r8a7791) Koelsch
Hans Verkuil says "The adv7511 on the Koelsch board has a 12 MHz fixed
clock for the CEC block. Specify this in the dts to enable CEC support."
* Add PFC support to RZ/G1E (r8a7745) SoC and add Ethernet and SCIF2
pins to SK-RZG1E board.
This allows the kernel to control multiplexed pins for Ethernet
and SCIF2 rather than relying on setup inherited at boot.
* tag 'renesas-dt2-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: dts: r8a7791: Use R-Car SATA Gen2 fallback compat string
ARM: dts: r8a7790: Use R-Car SATA Gen2 fallback compat string
ARM: dts: r8a7743: Add OPP table for frequency scaling
ARM: dts: r8a7743: Add APMU node and second CPU core
ARM: dts: koelsch: Add CEC clock for HDMI transmitter
ARM: dts: sk-rzg1e: add Ether pins
ARM: dts: sk-rzg1e: add SCIF2 pins
ARM: dts: r8a7745: add PFC support
ARM: dts: r8a7743: Add I2C DT support
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Use newly added R-Car SATA Gen2 fallback compat string
in the DT of the r8a7791 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before the fallback compat string is considered.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Use newly added R-Car SATA Gen2 fallback compat string
in the DT of the r8a7790 SoC.
This should have no run-time effect as the driver matches against
the per-SoC compat string before the fallback compat string is considered.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add needed information inside CPU0 for the generic cpufreq-cpu0 driver.
- clock-latency = 300 us
Approximate worst-case latency to do clock transition for every
OPPs. Using an arbitrary safe value similar to r8a7791(R-Car M2) Soc.
- operating-points = < kHz - uV >
List of 6 operating points. All of them are using the same voltage
since DVS is not supported in RZ/G1 Soc.
Note:This also fixes the below errors seen on kernel logs
[ 0.876877] cpu cpu0: dev_pm_opp_get_opp_count: OPP table not found (-19)
[ 0.883727] cpu cpu1: cpufreq_init: failed to get clk: -2
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add DT nodes for the Advanced Power Management Unit (APMU) and the
second CPU core. Use the enable-method to point out that the APMU
should be used for SMP support.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The adv7511 on the Koelsch board has a 12 MHz fixed clock
for the CEC block. Specify this in the dts to enable CEC support.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add the (previously omitted) Ether/PHY pin data to the SK-RZG1E board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add the (previously omitted) SCIF2 pin data to the SK-RZG1E board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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