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* RISC-V: Implement archrandom when Zkr is availableSamuel Ortiz2024-01-182-0/+81
* riscv: Optimize hweight API with Zbb extensionXiao Wang2024-01-182-1/+81
* riscv: add dependency among Image(.gz), loader(.bin), and vmlinuz.efiMasahiro Yamada2024-01-181-0/+2
* Merge patch series "riscv: ftrace: Miscellaneous ftrace improvements"Palmer Dabbelt2024-01-184-55/+195
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| * samples: ftrace: Add RISC-V support for SAMPLE_FTRACE_DIRECT[_MULTI]Song Shuai2024-01-181-0/+2
| * riscv: ftrace: Add DYNAMIC_FTRACE_WITH_DIRECT_CALLS supportSong Shuai2024-01-183-0/+18
| * riscv: ftrace: Make function graph use ftrace directlySong Shuai2024-01-183-56/+175
| * riscv: select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRYSong Shuai2024-01-181-0/+1
* | Merge patch series "RISC-V: Disable DWARF5 with known broken LLVM versions"Palmer Dabbelt2024-01-182-3/+15
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| * | riscv: Restrict DWARF5 when building with LLVM to known working versionsNathan Chancellor2024-01-181-0/+9
| * | riscv: Hoist linker relaxation disabling logic into KconfigNathan Chancellor2024-01-182-3/+6
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* | Merge patch series "riscv: Add fine-tuned checksum functions"Palmer Dabbelt2024-01-185-4/+510
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| * | riscv: Add checksum libraryCharlie Jenkins2024-01-183-0/+338
| * | riscv: Add checksum headerCharlie Jenkins2024-01-181-0/+82
| * | riscv: Add static key for misaligned accessesCharlie Jenkins2024-01-182-3/+89
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* | Merge patch series "riscv: support kernel-mode Vector"Palmer Dabbelt2024-01-1621-28/+838
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| * | riscv: vector: allow kernel-mode Vector with preemptionAndy Chiu2024-01-169-22/+286
| * | riscv: vector: use kmem_cache to manage vector contextAndy Chiu2024-01-163-2/+28
| * | riscv: vector: use a mask to write vstate_ctrlAndy Chiu2024-01-161-1/+2
| * | riscv: vector: do not pass task_struct into riscv_v_vstate_{save,restore}()Andy Chiu2024-01-165-13/+9
| * | riscv: fpu: drop SR_SD bit checkingAndy Chiu2024-01-161-2/+1
| * | riscv: lib: vectorize copy_to_user/copy_from_userAndy Chiu2024-01-166-1/+125
| * | riscv: sched: defer restoring Vector context for userAndy Chiu2024-01-168-5/+41
| * | riscv: Add vector extension XOR implementationGreentime Hu2024-01-164-0/+168
| * | riscv: vector: make Vector always available for softirq contextAndy Chiu2024-01-163-4/+19
| * | riscv: Add support for kernel mode vectorGreentime Hu2024-01-166-1/+182
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* | Merge patch series "riscv: mm: Fixup & Optimize COMPAT code"Palmer Dabbelt2024-01-112-2/+2
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| * | riscv: mm: Fixup compat arch_get_mmap_endGuo Ren2024-01-111-1/+1
| * | riscv: mm: Fixup compat mode boot failureGuo Ren2024-01-111-1/+1
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* | riscv: Fix an off-by-one in get_early_cmdline()Christophe JAILLET2024-01-111-2/+1
* | riscv: Add support for BATCHED_UNMAP_TLB_FLUSHAlexandre Ghiti2024-01-114-20/+73
* | riscv: Use hugepage mappings for vmemmapAlexandre Ghiti2024-01-111-1/+20
* | Merge patch series "riscv: errata: thead: use riscv_nonstd_cache_ops for CMO"Palmer Dabbelt2024-01-113-46/+74
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| * | riscv: errata: thead: use pa based instructions for CMOJisheng Zhang2024-01-101-12/+6
| * | riscv: errata: thead: use riscv_nonstd_cache_ops for CMOJisheng Zhang2024-01-103-46/+80
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* | Merge patch series "RISC-V SBI debug console extension support"Palmer Dabbelt2024-01-113-0/+77
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| * | RISC-V: Enable SBI based earlycon supportAnup Patel2024-01-101-0/+1
| * | RISC-V: Add SBI debug console helper routinesAnup Patel2024-01-102-0/+71
| * | RISC-V: Add stubs for sbi_console_putchar/getchar()Anup Patel2024-01-101-0/+5
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* | riscv: sbi: Introduce system suspend supportAndrew Jones2024-01-113-1/+54
* | Merge patch series "riscv: modules: Fix module loading error handling"Palmer Dabbelt2024-01-111-5/+9
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| * | riscv: Fix relocation_hashtable sizeCharlie Jenkins2024-01-101-1/+1
| * | riscv: Correctly free relocation hashtable on errorCharlie Jenkins2024-01-101-3/+7
| * | riscv: Fix module loading free orderCharlie Jenkins2024-01-101-1/+1
* | | Merge patch series "riscv: enable EFFICIENT_UNALIGNED_ACCESS and DCACHE_WORD_...Palmer Dabbelt2024-01-115-0/+89
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| * | | riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HWJisheng Zhang2024-01-104-0/+74
| * | | riscv: introduce RISCV_EFFICIENT_UNALIGNED_ACCESSJisheng Zhang2024-01-102-0/+15
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* | | Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"Palmer Dabbelt2024-01-104-0/+10
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| * | | riscv: hwprobe: export Zicond extensionClément Léger2024-01-102-0/+2
| * | | riscv: hwprobe: export Zacas ISA extensionClément Léger2024-01-102-0/+2
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