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* ARC: [plat-arcfpga] Static platform device for CONFIG_SERIAL_ARCVineet Gupta2013-02-154-0/+167
| | | | | | | | | | | | N.B. This is old style of hardcoding platform device specific info in code and it's instantiation thererof using platform_add_devices(). Subsequent patches replace this with DeviceTree based runtime probe. This patch has been retained just as an example of "don't-do-this" for newer kernel ports. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de>
* ARC: Boot #1: low-level, setup_arch(), /proc/cpuinfo, mem initVineet Gupta2013-02-158-0/+506
| | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* ARC: I/O and DMA MappingsVineet Gupta2013-02-156-0/+528
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Page Fault handlingVineet Gupta2013-02-151-0/+228
| | | | | | | | | | | | | | This includes recent changes to make handler "retry" and/or "killable" The killable (early exit) logic is loosely based on how SH implements it return if SIGKILL + either of VM_FAULT_OOM or VM_FAULT_RETRY which is different from Hexagon implementation which would NOT early exit for SIGKILL + VM_FAULT_OOM + !VM_FAULT_RETRY credits: Non executable stack support from Simon Spooner Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: TLB flush HandlingVineet Gupta2013-02-153-0/+356
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: MMU Exception HandlingVineet Gupta2013-02-155-0/+854
| | | | | | | | | * MMU I-TLB / D-TLB Miss Exceptions - Fast Path TLB Refill Handler - slowpath TLB creation via do_page_fault() -> update_mmu_cache() * Duplicate PD Exception Handler Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: MMU Context ManagementVineet Gupta2013-02-154-0/+262
| | | | | | | | | | | | ARC700 MMU provides for tagging TLB entries with a 8-bit ASID to avoid having to flush the TLB every task switch. It also allows for a quick way to invalidate all the TLB entries for task useful for: * COW sementics during fork() * task exit()ing Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Page Table ManagementVineet Gupta2013-02-153-0/+627
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Cache Flush ManagementVineet Gupta2013-02-155-0/+954
| | | | | | | | | * ARC700 has VIPT L1 Caches * Caches don't snoop and are not coherent * Given the PAGE_SIZE and Cache associativity, we don't support aliasing D$ configurations (yet), but do allow aliasing I$ configs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: [Review] Prevent incorrect syscall restartsVineet Gupta2013-02-152-4/+11
| | | | | | | | | | | | | | | | | | | | | Per Al Viro's "signals for dummies" https://lkml.org/lkml/2012/12/6/366 there are 3 golden rules for (not) restarting syscalls: " What we need to guarantee is * restarts do not happen on signals caught in interrupts or exceptions * restarts do not happen on signals caught in sigreturn() * restart should happen only once, even if we get through do_signal() many times." ARC Port already handled #1, this patch fixes #2 and #3. We use the additional state in pt_regs->orig_r8 to ckh if restarting has already been done once. Thanks to Al Viro for spotting this. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Al Viro <viro@ZenIV.linux.org.uk>
* ARC: [Review] Preparing to fix incorrect syscall restarts due to signalsVineet Gupta2013-02-154-19/+40
| | | | | | | | | | | | | | | | | | | | | | | | To avoid multiple syscall restarts (multiple signals) or no restart at all (sigreturn), we need just an extra bit of state "literally 1 bit" in struct pt_regs. orig_r8 is the best place to do this, however given the way it is encoded currently, we can't add anything simplistically. Current orig_r8: * syscalls -> 1 to NR_SYSCALLS * Exceptions -> NR_SYSCALLS + 1 * Break-point-> NR_SYSCALLS + 2 In new scheme it is a bit-field * lower short word contains the exact event type (and a new bit to represent restart semantics : if syscall was already / can't be restarted) * upper short word optionally containing the syscall num - needed by likes of tracehooks etc This patch only changes how orig_r8 is organised and nothing should change behaviourily. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Al Viro <viro@ZenIV.linux.org.uk>
* ARC: Signal handlingVineet Gupta2013-02-156-3/+449
| | | | | | | | | | | | | | | | | | | | Includes following fixes courtesy review by Al-Viro * Tracer poke to Callee-regs were lost Before going off into do_signal( ) we save the user-mode callee regs (as they are not saved by default as part of pt_regs). This is to make sure that that a Tracer (if tracing related signal) is able to do likes of PEEKUSR(callee-reg). However in return path we were simply discarding the user-mode callee regs, which would break a POKEUSR(callee-reg) from a tracer. * Issue related to multiple syscall restarts are addressed in next patch Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Al Viro <viro@ZenIV.linux.org.uk> Acked-by: Jonas Bonn <jonas@southpole.se>
* ARC: Timers/counters/delay managementVineet Gupta2013-02-117-0/+425
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARC700 includes 2 in-core 32bit timers TIMER0 and TIMER1. Both have exactly same capabilies. * programmable to count from TIMER<n>_CNT to TIMER<n>_LIMIT * for count 0 and LIMIT ~1, provides a free-running counter by auto-wrapping when limit is reached. * optionally interrupt when LIMIT is reached (oneshot event semantics) * rearming the interrupt provides periodic semantics * run at CPU clk ARC Linux uses TIMER0 for clockevent (periodic/oneshot) and TIMER1 for clocksource (free-running clock). Newer cores provide RTSC insn which gives a 64bit cpu clk snapshot hence is more apt for clocksource when available. SMP poses a bit of challenge for global timekeeping clocksource / sched_clock() backend: -TIMER1 based local clocks are out-of-sync hence can't be used (thus we default to jiffies based cs as well as sched_clock() one/both of which platform can override with it's specific hardware assist) -RTSC is only allowed in SMP if it's cross-core-sync (Kconfig glue ensures that) and thus usable for both requirements. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
* ARC: Process-creation/scheduling/idle-loopVineet Gupta2013-02-1110-8/+484
| | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Al Viro <viro@ZenIV.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de>
* ARC: Syscall support (no-legacy-syscall ABI)Vineet Gupta2013-02-118-0/+228
| | | | | | | | | This includes support for generic clone/for/vfork/execve Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Al Viro <viro@ZenIV.linux.org.uk> Acked-by: Arnd Bergmann <arnd@arndb.de>
* ARC: Non-MMU Exception HandlingVineet Gupta2013-02-112-7/+125
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Interrupt HandlingVineet Gupta2013-02-115-2/+152
| | | | | | | | | | This contains: -bootup arch IRQ init: init_IRQ(), arc_init_IRQ() -generic IRQ subsystem glue: arch_do_IRQ() -basic IRQ chip setup for in-core intc Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
* ARC: Low level IRQ/Trap/Exception HandlingVineet Gupta2013-02-112-0/+1066
| | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Al Viro <viro@ZenIV.linux.org.uk>
* ARC: String libraryVineet Gupta2013-02-118-0/+661
| | | | | | | | Hand optimised asm code for ARC700 pipeline. Originally written/optimized by Joern Rennecke Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Joern Rennecke <joern.rennecke@embecosm.com>
* ARC: Spinlock/rwlock/mutex primitivesVineet Gupta2013-02-113-0/+188
| | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* ARC: Fundamental ARCH data-types/definesVineet Gupta2013-02-1112-0/+685
| | | | | | | | | | | | | | | | | | | | * L1_CACHE_SHIFT * PAGE_SIZE, PAGE_OFFSET * struct pt_regs, struct user_regs_struct * struct thread_struct, cpu_relax(), task_pt_regs(), start_thread(), ... * struct thread_info, THREAD_SIZE, INIT_THREAD_INFO(), TIF_*, ... * BUG() * ELF_* * Elf_* To disallow user-space visibility into some of the core kernel data-types such as struct pt_regs, #ifdef __KERNEL__ which also makes the UAPI header spit (further patch in the series) to NOT export it to asm/uapi/ptrace.h Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Jonas Bonn <jonas.bonn@gmail.com> Cc: Al Viro <viro@ZenIV.linux.org.uk> Acked-by: Arnd Bergmann <arnd@arndb.de>
* ARC: Checksum/byteorder/swab routinesVineet Gupta2013-02-113-0/+217
| | | | | | | TBD: do_csum still needs to be written in asm Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* ARC: [optim] uaccess __{get,put}_user() optimisedVineet Gupta2013-02-111-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | Override asm-generic implementations. We basically gain on 2 fronts * checks for alignment no longer needed as we are only doing "unit" sized copies. (Careful observer could argue that While the kernel buffers are aligned, the user buffer in theory might not be - however in that case the user space is already broken when it tries to deref a hword/word straddling word boundary - so we are not making it any worse). * __copy_{to,from}_user( ) returns bytes that couldn't be copied, whereas get_user() returns 0 for success or -EFAULT (not size). Thus the code to do leftover bytes calculation can be avoided as well. The savings were significant: ~17k of code. bloat-o-meter vmlinux_uaccess_pre vmlinux_uaccess_post add/remove: 0/4 grow/shrink: 8/118 up/down: 1262/-18758 (-17496) ^^^^^^^^^ Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* ARC: uaccess friendsVineet Gupta2013-02-113-0/+733
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Atomic/bitops/cmpxchg/barriersVineet Gupta2013-02-115-0/+967
| | | | | | | This covers the UP / SMP (with no hardware assist for atomic r-m-w) as well as ARC700 LLOCK/SCOND insns based. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: irqflags - Interrupt enabling/disabling at in-core intcVineet Gupta2013-02-113-0/+295
| | | | | | | | | | | | | | | | | | | | ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels" of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts. CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2) to globally enable (or disable) all IRQs at a level. Hence the implementation of arch_local_irq_{save,restore,enable,disable}( ) The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence the use of LR/SR instructions. Further, E1/E2 bits in there can only be updated using the FLAG insn. The intc supports 32 interrupts - and per IRQ enabling is controlled by a bit in the AUX_IENABLE register, hence the implmentation of arch_{,un}mask_irq( ) routines. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
* ARC: Build system: Makefiles, Kconfig, Linker scriptVineet Gupta2013-02-1114-0/+816
| | | | | | | | | | | | | | | | | | | | Arnd in his review pointed out that arch Kconfig organisation has several deficiencies: * Build time entries for things which can be runtime extracted from DT (e.g. SDRAM size, core clk frequency..) * Not multi-platform-image-build friendly (choice .. endchoice constructs) * cpu variants support (750/770) is exclusive. The first 2 have been fixed in subsequent patches. Due to the nature of the 750 and 770, it is not possible to build for both together, w/o special runtime glue code which would hurt performance. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Sam Ravnborg <sam@ravnborg.org> Acked-by: Sam Ravnborg <sam@ravnborg.org>
* ARC: Generic HeadersVineet Gupta2013-01-282-0/+67
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* Merge git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2013-01-251-0/+2
|\ | | | | | | | | | | | | Pull kvm fixlet from Marcelo Tosatti. * git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: PPC: Emulate dcbf
| * KVM: PPC: Emulate dcbfAlexander Graf2013-01-181-0/+2
| | | | | | | | | | | | | | | | | | | | Guests can trigger MMIO exits using dcbf. Since we don't emulate cache incoherent MMIO, just do nothing and move on. Reported-by: Ben Collins <ben.c@servergy.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Ben Collins <ben.c@servergy.com> CC: stable@vger.kernel.org
* | Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds2013-01-246-27/+26
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM fixes from Russell King: "A number of fixes: Patrik found a problem with preempt counting in the VFP assembly functions which can cause the preempt count to be upset. Nicolas fixed a problem with the parsing of the DT when it straddles a 1MB boundary. Subhash Jadavani reported a problem with sparsemem and our highmem support for cache maintanence for DMA areas, and TI found a bug in their strongly ordered memory mapping type. Also, three fixes by way of Will Deacon's tree from Dave Martin for instruction compatibility and Marc Zyngier to fix hypervisor boot mode issues." * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7629/1: mm: Fix missing XN flag for for MT_MEMORY_SO ARM: DMA: Fix struct page iterator in dma_cache_maint() to work with sparsemem ARM: 7628/1: head.S: map one extra section for the ATAG/DTB area ARM: 7627/1: Predicate preempt logic on PREEMP_COUNT not PREEMPT alone ARM: virt: simplify __hyp_stub_install epilog ARM: virt: boot secondary CPUs through the right entry point ARM: virt: Avoid bx instruction for compatibility with <=ARMv4
| * \ Merge branch 'for-rmk/virt/hyp-boot/fixes' of ↵Russell King2013-01-19305-1068/+1129
| |\ \ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into fixes
| | * | ARM: virt: simplify __hyp_stub_install epilogMarc Zyngier2013-01-101-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | __hyp_stub_install duplicates quite a bit of safe_svcmode_maskall by forcing the CPU back to SVC. This is unnecessary, as safe_svcmode_maskall is called just after. Furthermore, the way we build SPSR_hyp is buggy as we fail to mask the interrupts, leading to interesting behaviours on TC2 + UEFI. The fix is to simply remove this code and rely on safe_svcmode_maskall to do the right thing. Cc: <stable@vger.kernel.org> Reviewed-by: Dave Martin <dave.martin@linaro.org> Reported-by: Harry Liebel <harry.liebel@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * | ARM: virt: boot secondary CPUs through the right entry pointMarc Zyngier2013-01-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secondary CPUs should use the __hyp_stub_install_secondary entry point, so boot mode inconsistencies can be detected. Cc: <stable@vger.kernel.org> Acked-by: Dave Martin <dave.martin@linaro.org> Reported-by: Ian Molton <ian.molton@collabora.co.uk> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * | ARM: virt: Avoid bx instruction for compatibility with <=ARMv4Dave Martin2013-01-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Non-T variants of ARMv4 do not support the bx instruction. However, __hyp_stub_install is always called from the same instruction set used to build the bulk of the kernel, so bx should not be necessary. This patch uses the traditional "mov pc" instead of bx. Cc: <stable@vger.kernel.org> Signed-off-by: Dave Martin <dave.martin@linaro.org> [will: fixed up remaining bx instruction] Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | ARM: 7629/1: mm: Fix missing XN flag for for MT_MEMORY_SOSantosh Shilimkar2013-01-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 8fb54284ba6a {ARM: mm: Add strongly ordered descriptor support} added XN flag at section level but missed it at PTE level. Fix it by adding the L_PTE_XN to MT_MEMORY_SO PTE descriptor. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: DMA: Fix struct page iterator in dma_cache_maint() to work with sparsememRussell King2013-01-191-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Subhash Jadavani reported this partial backtrace: Now consider this call stack from MMC block driver (this is on the ARMv7 based board): [<c001b50c>] (v7_dma_inv_range+0x30/0x48) from [<c0017b8c>] (dma_cache_maint_page+0x1c4/0x24c) [<c0017b8c>] (dma_cache_maint_page+0x1c4/0x24c) from [<c0017c28>] (___dma_page_cpu_to_dev+0x14/0x1c) [<c0017c28>] (___dma_page_cpu_to_dev+0x14/0x1c) from [<c0017ff8>] (dma_map_sg+0x3c/0x114) This is caused by incrementing the struct page pointer, and running off the end of the sparsemem page array. Fix this by incrementing by pfn instead, and convert the pfn to a struct page. Cc: <stable@vger.kernel.org> Suggested-by: James Bottomley <JBottomley@Parallels.com> Tested-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 7628/1: head.S: map one extra section for the ATAG/DTB areaNicolas Pitre2013-01-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently use a temporary 1MB section aligned to a 1MB boundary for mapping the provided device tree until the final page table is created. However, if the device tree happens to cross that 1MB boundary, the end of it remains unmapped and the kernel crashes when it attempts to access it. Given no restriction on the location of that DTB, it could end up with only a few bytes mapped at the end of a section. Solve this issue by mapping two consecutive sections. Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Sascha Hauer <s.hauer@pengutronix.de> Tested-by: Tomasz Figa <t.figa@samsung.com> Cc: stable@vger.kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 7627/1: Predicate preempt logic on PREEMP_COUNT not PREEMPT aloneStephen Boyd2013-01-162-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patrik Kluba reports that the preempt count becomes invalid due to the preempt_enable() call being unbalanced with a preempt_disable() call in the vfp assembly routines. This happens because preempt_enable() and preempt_disable() update preempt counts under PREEMPT_COUNT=y but the vfp assembly routines do so under PREEMPT=y. In a configuration where PREEMPT=n and DEBUG_ATOMIC_SLEEP=y, PREEMPT_COUNT=y and so the preempt_enable() call in VFP_bounce() keeps subtracting from the preempt count until it goes negative. Fix this by always using PREEMPT_COUNT to decided when to update preempt counts in the ARM assembly code. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reported-by: Patrik Kluba <pkluba@dension.com> Tested-by: Patrik Kluba <pkluba@dension.com> Cc: <stable@vger.kernel.org> # 2.6.30 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | Merge tag 'fixes-for-linus2' of ↵Linus Torvalds2013-01-2440-180/+176
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "Here's a long-pending fixes pull request for arm-soc (I didn't send one in the -rc4 cycle). The larger deltas are from: - A fixup of error paths in the mvsdio driver - Header file move for a driver that hadn't been properly converted to multiplatform on i.MX, which was causing build failures when included - Device tree updates for at91 dealing mostly with their new pinctrl setup merged in 3.8 and mistakes in those initial configs The rest are the normal mix of small fixes all over the place; sunxi, omap, imx, mvebu, etc, etc." * tag 'fixes-for-linus2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (40 commits) mfd: vexpress-sysreg: Don't skip initialization on probe ARM: vexpress: Enable A7 cores in V2P-CA15_A7's Device Tree ARM: vexpress: extend the MPIDR range used for pen release check ARM: at91/dts: correct comment in at91sam9x5.dtsi for mii ARM: at91/at91_dt_defconfig: add at91sam9n12 SoC to DT defconfig ARM: at91/at91_dt_defconfig: remove memory specification to cmdline ARM: at91/dts: add macb mii pinctrl config for kizbox ARM: at91: rm9200: remake the BGA as default version ARM: at91: fix gpios on i2c-gpio for RM9200 DT ARM: at91/at91sam9x5 DTS: add SCK USART pins ARM: at91/at91sam9x5 DTS: correct wrong PIO BANK values on u(s)arts ARM: at91/at91-pinctrl documentation: fix typo and add some details ARM: kirkwood: fix missing #interrupt-cells property mmc: mvsdio: use devm_ API to simplify/correct error paths. clk: mvebu/clk-cpu.c: fix memory leakage ARM: OMAP2+: omap4-panda: add UART2 muxing for WiLink shared transport ARM: OMAP2+: DT node Timer iteration fix ARM: OMAP2+: Fix section warning for omap_init_ocp2scp() ARM: OMAP2+: fix build break for omapdrm ARM: OMAP2: Fix missing omap2xxx_clkt_vps_late_init function calls ...
| * \ \ \ Merge branch 'vexpress/fixes' of git://git.linaro.org/people/pawelmoll/linux ↵Olof Johansson2013-01-242-3/+1
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into fixes From Pawel Moll: - makes the V2P-CA15_A7 (a.k.a. TC2) work with 3.8 kernels - improves vexpress-sysreg.c behaviour on arm64 platforms * 'vexpress/fixes' of git://git.linaro.org/people/pawelmoll/linux: mfd: vexpress-sysreg: Don't skip initialization on probe ARM: vexpress: Enable A7 cores in V2P-CA15_A7's Device Tree ARM: vexpress: extend the MPIDR range used for pen release check
| | * | | | ARM: vexpress: Enable A7 cores in V2P-CA15_A7's Device TreePawel Moll2013-01-241-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the kernel is able to cope with multiple clusters, uncomment the A7 cores in the Device Tree for V2P-CA15_A7 tile, making all 5 cores available to the user. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
| | * | | | ARM: vexpress: extend the MPIDR range used for pen release checkLorenzo Pieralisi2013-01-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In ARM multi-cluster systems the MPIDR affinity level 0 cannot be used as a single cpu identifier, affinity levels 1 and 2 must be taken into account as well. This patch extends the MPIDR usage to affinity levels 1 and 2 in versatile secondary cores start up code in order to compare the passed pen_release value with the full-blown affinity mask. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Pawel Moll <pawel.moll@arm.com>
| * | | | | Merge tag 'at91-fixes' of git://github.com/at91linux/linux-at91 into fixesOlof Johansson2013-01-245-23/+48
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Nicolas Ferre: Here are fixes for AT91 that are mainly related to device tree. One RM9200 setup option is the only C code change. Some documentation changes can clarify the pinctrl use. Then, some defconfig modifications are allowing the affected platforms to boot. * tag 'at91-fixes' of git://github.com/at91linux/linux-at91: ARM: at91/dts: correct comment in at91sam9x5.dtsi for mii ARM: at91/at91_dt_defconfig: add at91sam9n12 SoC to DT defconfig ARM: at91/at91_dt_defconfig: remove memory specification to cmdline ARM: at91/dts: add macb mii pinctrl config for kizbox ARM: at91: rm9200: remake the BGA as default version ARM: at91: fix gpios on i2c-gpio for RM9200 DT ARM: at91/at91sam9x5 DTS: add SCK USART pins ARM: at91/at91sam9x5 DTS: correct wrong PIO BANK values on u(s)arts ARM: at91/at91-pinctrl documentation: fix typo and add some details
| | * | | | | ARM: at91/dts: correct comment in at91sam9x5.dtsi for miiDouglas Gilbert2013-01-231-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Concerning pinctrl_macb0_rmii_mii, values were okay, but not comments. Signed-off-by: Douglas Gilbert <dgilbert@interlog.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | | | | ARM: at91/at91_dt_defconfig: add at91sam9n12 SoC to DT defconfigNicolas Ferre2013-01-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reported-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | | | | ARM: at91/at91_dt_defconfig: remove memory specification to cmdlineNicolas Ferre2013-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need for this cmdline option as we are using DT. Moreover this defconfig is targeted to multiple SoC/boards: this option was nonsense. Reported-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | | | | ARM: at91/dts: add macb mii pinctrl config for kizboxBoris BREZILLON2013-01-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch overrides default macb pinctrl config defined in at91sam9260.dtsi (pinctrl_macb_rmii) with kizbox board config (pinctrl_macb_rmii + pinctrl_macb_rmii_mii_alt). Signed-off-by: Boris BREZILLON <linux-arm@overkiz.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | | | | ARM: at91: rm9200: remake the BGA as default versionJean-Christophe PLAGNIOL-VILLARD2013-01-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make BGA as the default version as we are supposed to just have to specify when we use the PQFP version. Issue was existing since commit: 3e90772 (ARM: at91: fix at91rm9200 soc subtype handling). Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: stable <stable@vger.kernel.org> [v3.3] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
| | * | | | | ARM: at91: fix gpios on i2c-gpio for RM9200 DTJoachim Eastwood2013-01-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Joachim Eastwood <manabian@gmail.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-02-03 22:18:58 +0100