| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |\
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX DT changes with new clock for 5.3:
- This is a set of device tree changes with new clocks - adding
clock info for i.MX8 GPIO and SNVS RTC device.
* tag 'imx-dt-clkdep-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: imx8mq: add clock for SNVS RTC node
arm64: dts: imx8mm: add clock for SNVS RTC node
arm64: dts: imx8mm: add clock for GPIO node
clk: imx8m: Add GIC clock
dt-bindings: clock: imx8m: Add GIC clock
clk: imx8mm: add SNVS clock to clock tree
dt-bindings: clock: imx8mm: Add SNVS clock
clk: imx8mq: add SNVS clock to clock tree
dt-bindings: clock: imx8mq: Add SNVS clock
clk: imx8mm: add GPIO clocks to clock tree
dt-bindings: clock: imx8mm: Add GPIO clocks
Signed-off-by: Olof Johansson <olof@lixom.net>
|
| | |
| |
| |
| |
| |
| |
| |
| |
| | |
i.MX8MQ has clock gate for SNVS module, add clock info to SNVS
RTC node for clock management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
| | |
| |
| |
| |
| |
| |
| |
| |
| | |
i.MX8MM has clock gate for SNVS module, add clock info to SNVS
RTC node for clock management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
| | |
| |
| |
| |
| |
| |
| |
| |
| | |
i.MX8MM has clock gate for each GPIO bank, add clock info
to GPIO node for clock management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
| |\ \
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This is the pxa devicetree changes for 5.3 cycle :
- devicetree pinmux support for bias on pxa3xx
- devicetree pinmux bias usage for raumfeld
* tag 'pxa-dt-5.3' of https://github.com/rjarzmik/linux:
ARM: dts: pxa300-raumfeld-speaker-one: add channel output mapping for STA320
ARM: pxa: raumfeld-common: fix comments in gpio_keys pinctrl node
ARM: pxa: raumfeld-controller: add pinctrl for charger pins
ARM: pxa: raumfeld-controller: fix 'dock detect' GPIO key
ARM: pxa3xx: dts: Add defines for pinctrl-single,bias-pull{up,down}
Signed-off-by: Olof Johansson <olof@lixom.net>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | | |
These settings are needed to make the hardware operable.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | | |
Careless oversight.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The PEN2 line needs to be pulled up for the charger to enter high-current
mode. Do this with a static pull on the GPIO.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | | |
The dock detection input key is active low. Also add a pinmux for it.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
|
| | |/
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
This allows users of the pinctrl driver to specify either
pinctrl-single,bias-pullup = MPF_PULL_UP;
or
pinctrl-single,bias-pulldown = MPF_PULL_DOWN;
To activate the pull bits in the MFP registers.
Signed-off-by: Daniel Mack <daniel@zonque.org>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
|
| |\ \
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt
AT91 DT for 5.3
- switch to new sckc bindings
- convert soc bindings to json-schema
* tag 'at91-5.3-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
dt-bindings: arm: Convert Atmel board/soc bindings to json-schema
ARM: dts: at91: sama5d3: switch to new sckc bindings
ARM: dts: at91: at91sam9rl: switch to new sckc bindings
ARM: dts: at91: at91sam9g45: switch to new sckc bindings
ARM: dts: at91: at91sam9x5: switch to new sckc bindings
ARM: dts: at91sam9261ek: remove unused chosen nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Remove the child nodes of the sckc as they are not necessary anymore.
Also, switch to the new atmel,sama5d3-sckc compatible string to use the
proper startup time for the RC oscillator (500 µs instead of 75).
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
| | | |
| | |
| | |
| | |
| | |
| | | |
Remove the child nodes of the sckc as they are not necessary anymore.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
| | | |
| | |
| | |
| | |
| | |
| | | |
Remove the child nodes of the sckc as they are not necessary anymore.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
| | | |
| | |
| | |
| | |
| | |
| | | |
Remove the child nodes of the sckc as they are not necessary anymore.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
| | |/
| |
| |
| |
| |
| |
| | |
The chosen clocksource and clockevent bindings have never been accepted and
parsed, remove them.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
| |\ \
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.3-rc1
This contains the bulk of the Tegra changes this cycle. It has a bunch
of improvements across almost all boards. These are mostly small and not
too exciting additions.
Most notably perhaps is the continuation of Jetson Nano support, which
is now mostly on feature parity with Jetson TX1.
* tag 'tegra-for-5.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (28 commits)
arm64: tegra: Enable PCIe slots in P2972-0000 board
arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT
arm64: tegra: Add PEX DPD states as pinctrl properties
arm64: tegra: Enable ACONNECT, ADMA and AGIC
arm64: tegra: Add ACONNECT, ADMA and AGIC nodes
arm64: tegra: Sort device tree nodes alphabetically
arm64: tegra: Fix Jetson Nano GPU regulator
arm64: tegra: Update Jetson TX1 GPU regulator timings
arm64: tegra: Fix AGIC register range
arm64: tegra: Add INA3221 channel info for Jetson TX2
arm64: tegra: Enable PWM on Jetson Nano
arm64: tegra: Enable CPU sleep on Jetson Nano
arm64: tegra: Add ID EEPROMs on Jetson Nano
arm64: tegra: Add ID EEPROM for Jetson TX2 Developer Kit
arm64: tegra: Add ID EEPROM for Jetson TX2 module
arm64: tegra: Add ID EEPROM for Jetson TX1 Developer Kit
arm64: tegra: Add ID EEPROM for Jetson TX1 module
arm64: tegra: Don't use architected timer for suspend on Tegra210
arm64: tegra: Mark architected timer as always on
arm64: tegra: Add pin control states for I2C on Tegra186
...
Signed-off-by: Olof Johansson <olof@lixom.net>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Enable PCIe controller nodes to enable respective PCIe slots on
P2972-0000 board. Following is the ownership of slots by different
PCIe controllers.
Controller-0 : M.2 Key-M slot
Controller-1 : On-board Marvell eSATA controller
Controller-3 : M.2 Key-E slot
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra194 SoC contains six PCIe controllers and twenty P2U instances
grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us)
and NVIDIA High Speed (NVHS-8 P2Us) respectively.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Add PEX deep power down states as pinctrl properties to set in PCIe driver.
In Tegra210, BIAS pads are not in power down mode when clamps are applied.
To set the pads in DPD, pass the PEX DPD states as pinctrl properties to
PCIe driver.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Enable ACONNECT, ADMA and AGIC devices on Jetson TX2 and Jetson AGX
Xavier.
Verified driver probe path and devices get registered fine.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Add device tree nodes for the ACONNECT, ADMA and AGIC devices on
Tegra186 and Tegra194.
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | | |
Device tree nodes without unit-address are to be sorted alphabetically.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
There are a few issues with the GPU regulator defined for Jetson Nano
which are:
1. The GPU regulator is a PWM based regulator and not a fixed voltage
regulator.
2. The output voltages for the GPU regulator are not correct.
3. The regulator enable ramp delay is too short for the regulator and
needs to be increased. 2ms should be sufficient.
4. This is the same regulator used on Jetson TX1 and so make the ramp
delay and settling time the same as Jetson TX1.
Cc: stable@vger.kernel.org
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Fixes: 6772cd0eacc8 ("arm64: tegra: Add NVIDIA Jetson Nano Developer Kit support")
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The GPU regulator enable ramp delay for Jetson TX1 is set to 1ms which
not sufficient because the enable ramp delay has been measured to be
greater than 1ms. Furthermore, the downstream kernels released by NVIDIA
for Jetson TX1 are using a enable ramp delay 2ms and a settling delay of
160us. Update the GPU regulator enable ramp delay for Jetson TX1 to be
2ms and add a settling delay of 160us.
Cc: stable@vger.kernel.org
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Fixes: 5e6b9a89afce ("arm64: tegra: Add VDD_GPU regulator to Jetson TX1")
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The Tegra AGIC interrupt controller is an ARM GIC400 interrupt
controller. Per the ARM GIC device-tree binding, the first address
region is for the GIC distributor registers and the second address
region is for the GIC CPU interface registers. The address space for
the distributor registers is 4kB, but currently this is incorrectly
defined as 8kB for the Tegra AGIC and overlaps with the CPU interface
registers. Correct the address space for the distributor to be 4kB.
Cc: stable@vger.kernel.org
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Fixes: bcdbde433542 ("arm64: tegra: Add AGIC node for Tegra210")
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
There are four INA3221 chips on the Jetson TX2 (p3310 + p2771).
And each INA3221 chip has three input channels to monitor power.
So this patch adds these 12 channels to the DT of Jetson TX2, by
following the DT binding of INA3221 and official documents from
https://developer.nvidia.com/embedded/downloads
tegra186-p3310:
https://developer.nvidia.com/embedded/dlc/jetson-tx2-series-modules-oem-product-design-guide
tegra186-p2771-0000:
http://developer.nvidia.com/embedded/dlc/jetson-tx1-tx2-developer-kit-carrier-board-spec-20180618
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | | |
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Jetson Nano implements CPU sleep via PSCI, much like any of the other
Tegra X1 platforms. Enable the sleep states to allow the CPU to go into
lower power states when idle.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The Jetson Nano has two ID EEPROMs, one for the module and another for
the carrier board. Add both to the device tree so that they can be read
from at runtime.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
There is an ID EEPROM on the Jetson TX2 carrier board, part of the
Jetson TX2 Developer Kit, that exposes information that can be used to
identify the carrier board. Add the device tree node so that operating
systems can access this EEPROM.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
There is an ID EEPROM in the Jetson TX2 module that stores various bits
of information to indentify the module. Add the device tree node so that
operating systems can access this EEPROM.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
There is an ID EEPROM on the Jetson TX1 carrier board, part of the
Jetson TX1 Developer Kit, that exposes information that can be used to
identify the carrier board. Add the device tree node so that operating
systems can access this EEPROM.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
There is an ID EEPROM in the Jetson TX1 module that stores various bits
of information to indentify the module. Add the device tree node so that
operating systems can access this EEPROM.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Due to an integration issue the architected timer on Tegra210 does not
remain on during system suspend (a.k.a. SC7). Mark it accordingly so
that it isn't considered as a means to track suspend time.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The architected timer on Tegra186 and Tegra194 is in an always on power
partition and its reference clock will always run, so mark the timer as
always on.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Two of the Tegra I2C controllers share pads with the DPAUX controllers.
In order for the I2C controllers to use these pads, they have to be set
into I2C mode. Use the I2C and off pin control states defined in the DT
nodes for DPAUX as "default" and "idle" states, respectively. This
ensures that the I2C controller driver can properly configure the pins
when it needs to perform I2C transactions.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Tegra186 has two CPU clusters with its own cache hierarchy. This patch
adds them with the cache information of each of the CPUs.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
The GPIO expanders on Jetson TX2 are powered by the VDD_1V8 and
VDD_3V3_SYS supplies, respectively. Model this in device tree so that
the correct supplies are referenced.
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Jetson Nano, Jetson TX1 and Jetson TX2 all are named "Developer Kit" and
Jetson AGX Xavier is the odd one out. It's officially also called the
"Developer Kit", not "Development Kit", so make it consistent with the
rest.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
P2888 is the internal part number for the Jetson AGX Xavier module.
Clarify that using the DT model property.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
P3310 is the internal part number for the Jetson TX2 module. Clarify
that using the DT model property.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
P2771 is the internal part number for the Jetson TX2 Developer Kit.
Clarify that using the DT model property.
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| | |/
| |
| |
| |
| |
| |
| |
| | |
In order to move away from misleadingly generic definitions of the GPIO
macros, use the Tegra186-specific prefix. These are the last remaining
occurrences. The generic definitions can be removed after this.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| |\ \
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT updates for v5.3, round 1
Highlights:
----------
MPU part:
-Add stm32mp157a-avenger board support:
This board embeds a STM32MP157a SOC with AC package (TFBGA361, 148 ios)
, 1024MB of DDR3 and STPMIC1A pmic . Several connections are available on this boards:
2x Type A (USB 2.0) Host and 1x Micro B (USB 2.0) OTG, ethernet
10/100/1000, WiFi 5 GHz & 2.4GHz, ...
-Add STMFX support en stm32mp157c-ev1 and enable joystick connected on
it.
-Add I2S and SAI support on stm32mp157c.
-Add and enable support of Vivante GPU on stm32mp157 ED1 and DK1 boards
(EV1 and DK2 inherit of it).
-Add camera support:
-Add DCMI support on stm32mp157c SOC
-Enabled OV5640 camera support on stm32mp157c-ev1 board
-Enable hdmi bridge sii9022 & display controller on stm32mp157c-dk1
board.
MCU part:
-Add STMFX support en stm32746g-eval and enable connections on it:
leds and joystick
* tag 'stm32-dt-for-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (27 commits)
ARM: dts: stm32: replace rgmii mode with rgmii-id on stm32mp15 boards
ARM: dts: stm32: Add Avenger96 devicetree support based on STM32MP157A
dt-bindings: arm: stm32: Document Avenger96 devicetree binding
dt-bindings: arm: stm32: Convert STM32 SoC bindings to DT schema
ARM: dts: stm32: Add missing pinctrl definitions for STM32MP157
ARM: dts: stm32: add sai id registers to stm32mp157c
ARM: dts: stm32: add power supply of rm68200 on stm32mp157c-ev1
ARM: dts: stm32: enable display on stm32mp157c-dk1 board
ARM: dts: stm32: Add I2C 1 config for stm32mp157a-dk1
ARM: dts: stm32: enable OV5640 camera on stm32mp157c-ev1 board
ARM: dts: stm32: add DCMI pins to stm32mp157c
ARM: dts: stm32: add DCMI camera interface support on stm32mp157c
ARM: dts: stm32: enable Vivante GPU support on stm32mp157a-dk1 board
ARM: dts: stm32: enable Vivante GPU support on stm32mp157c-ed1 board
ARM: dts: stm32: Add Vivante GPU support on STM32MP157c
ARM: dts: stm32: add i2s pins muxing on stm32mp157
ARM: dts: stm32: add i2s support on stm32mp157c
ARM: dts: stm32: add sai pins muxing on stm32mp157
ARM: dts: stm32: add sai support on stm32mp157c
ARM: dts: stm32: add jedec compatible for nor flash on stm32mp157c-ev1
...
Signed-off-by: Olof Johansson <olof@lixom.net>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
On disco and eval board, Tx and Rx delay are applied (pull-up of 4.7k
put on VDD) so which correspond to RGMII-ID mode with internal RX and TX
delays provided by the PHY, the MAC should not add the RX or TX delays
in this case
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Add devicetree support for Avenger96 board based on STM32MP157A MPU
from ST Micro. This board is one of the 96Boards Consumer Edition board
from Arrow Electronics and has the following features:
SoC: STM32MP157AAC
PMIC: STPMIC1A
RAM: 1024 Mbyte @ 533MHz
Storage: eMMC v4.51: 8 Gbyte
microSD Socket: UHS-1 v3.01
Ethernet Port: 10/100/1000 Mbit/s, IEEE 802.3 Compliant
Wireless: WiFi 5 GHz & 2.4GHz IEEE 802.11a/b/g/n/ac
Bluetooth®v4.2 (BR/EDR/BLE)
USB: 2x Type A (USB 2.0) Host and 1x Micro B (USB 2.0) OTG
Display: HDMI: WXGA (1366x768)@ 60 fps, HDMI 1.4
LED: 4x User LED, 1x WiFi LED, 1x BT LED
More information about this board can be found in 96Boards website:
https://www.96boards.org/product/avenger96/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | | |
Add missing pinctrl definitions for STM32MP157 MPU.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Add identification registers to address range
of SAI DT parent node, for stm32mp157c.
Signed-off-by: Olivier Moysan <olivier.moysan@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
|
| | | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
This patch adds a new property (power-supply) to panel rm68200 (raydium)
on stm32mp157c-ev1.
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
|
