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* Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-04-0310-47/+123
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 5965/1: Fix soft lockup in at91 udc driver ARM: 6006/1: ARM: Use the correct NOP size in memmove for Thumb-2 kernel builds ARM: 6005/1: arm: kprobes: fix register corruption with jprobes ARM: 6003/1: removing compilation warning from pl061.h ARM: 6001/1: removing compilation warning comming from clkdev.h ARM: 6000/1: removing compilation warning comming from <asm/irq.h> ARM: 5999/1: Including device.h and resource.h header files in linux/amba/bus.h ARM: 5997/1: ARM: Correct the VFPv3 detection ARM: 5996/1: ARM: Change the mandatory barriers implementation (4/4) ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4) ARM: 5994/1: ARM: Add outer_cache_fns.sync function pointer (2/4) ARM: 5993/1: ARM: Move the outer_cache definitions into a separate file (1/4)
| * ARM: 6006/1: ARM: Use the correct NOP size in memmove for Thumb-2 kernel buildsCatalin Marinas2010-03-291-2/+2
| | | | | | | | | | | | | | | | | | | | When compiling the kernel to Thumb-2, using a 16-bit NOP in the memmove() implementation causes the preceding ADD PC instruction to branch incorrectly in the middle of a 32-bit LDR or STR instruction. The memmove() code is now similar to the memcpy() template. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 6005/1: arm: kprobes: fix register corruption with jprobesMika Westerberg2010-03-291-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation of jprobes allocates empty pt_regs from the stack which is then passed to kprobe_handler() and eventually to singlestep(). Now when instruction being simulated is STMFD (like in normal function prologues without CONFIG_FRAME_POINTER), stores using SP actually write over top of the fabricated pt_regs structure. This can be reproduced for example by using LKDTM module: # modprobe lkdtm # mount -t debugfs none /sys/kernel/debug # echo PANIC > /sys/kernel/debug/provoke-crash/INT_HW_IRQ_EN after this, it fails with corrupted registers (before the requested crash would occur): lkdtm: Crash point INT_HW_IRQ_EN of type PANIC hit, trigger in 9 rounds lkdtm: Crash point INT_HW_IRQ_EN of type PANIC hit, trigger in 8 rounds Internal error: Oops - undefined instruction: 0 [#1] last sysfs file: /sys/devices/platform/serial8250.0/sleep_timeout Modules linked in: lkdtm CPU: 0 Not tainted (2.6.34-rc2 #69) PC is at irq_desc+0x1638/0xeeb0 LR is at 0x25 pc : [<c050b428>] lr : [<00000025>] psr: c80a0013 sp : ce94bd60 ip : c050b3e8 fp : a0000013 r10: c0aa453c r9 : cf5d4000 r8 : ce9a1822 r7 : c050b424 r6 : 00000025 r5 : c039d8f8 r4 : c050b3e8 r3 : 00000001 r2 : cf4d0440 r1 : c039d8f8 r0 : 00000020 Flags: NZcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user Control: 10c5387d Table: 8e804019 DAC: 00000015 Process sh (pid: 496, stack limit = 0xce94a2e8) Stack: (0xce94bd60 to 0xce94c000) [...] Code: 000002cd 00000000 00000000 00000001 (dead4ead) ---[ end trace 2b46d5f2b682f370 ]--- Kernel panic - not syncing: Fatal exception in interrupt This patch allocates enough space (2 * sizeof(struct pt_regs)) from the stack to prevent such corruption. Signed-off-by: Mika Westerberg <ext-mika.1.westerberg@nokia.com> Acked-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 6001/1: removing compilation warning comming from clkdev.hviresh kumar2010-03-291-0/+1
| | | | | | | | | | | | | | | | clkdev.h is using struct device *. Due to this compilation warning is comming. Removing this warning. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 6000/1: removing compilation warning comming from <asm/irq.h>viresh kumar2010-03-291-0/+1
| | | | | | | | | | | | | | | | | | irq.h is using struct pt_regs *. Due to this compilation warning is comming. Removing this warning by adding declaration of struct pt_regs. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5997/1: ARM: Correct the VFPv3 detectionCatalin Marinas2010-03-281-1/+1
| | | | | | | | | | | | | | | | A CPU has VFPv3 hardware if the FPSID[19:16] bits are 2 or more. Currently Linux was only checking for 3 or more. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5996/1: ARM: Change the mandatory barriers implementation (4/4)Catalin Marinas2010-03-252-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mandatory barriers (mb, rmb, wmb) are used even on uniprocessor systems for things like ordering Normal Non-cacheable memory accesses with DMA transfer (via Device memory writes). The current implementation uses dmb() for mb() and friends but this is not sufficient. The DMB only ensures the relative ordering of the observability of accesses by other processors or devices acting as masters. In case of DMA transfers started by writes to device memory, the relative ordering is not ensured because accesses to slave ports of a device are not considered observable by the DMB definition. A DSB is required for the data to reach the main memory (even if mapped as Normal Non-cacheable) before the device receives the notification to begin the transfer. Furthermore, some L2 cache controllers (like L2x0 or PL310) buffer stores to Normal Non-cacheable memory and this would need to be drained with the outer_sync() function call. The patch also allows platforms to define their own mandatory barriers implementation by selecting CONFIG_ARCH_HAS_BARRIERS and providing a mach/barriers.h file. Note that the SMP barriers are unchanged (being DMBs as before) since they are only guaranteed to work with Normal Cacheable memory. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)Catalin Marinas2010-03-252-0/+11
| | | | | | | | | | | | | | | | The L2x0 cache controllers need to explicitly drain their write buffer even for Normal Noncacheable memory accesses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5994/1: ARM: Add outer_cache_fns.sync function pointer (2/4)Catalin Marinas2010-03-252-0/+20
| | | | | | | | | | | | | | | | | | This patch introduces the outer_cache_fns.sync function pointer together with the OUTER_CACHE_SYNC config option that can be used to drain the write buffer of the outer cache. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5993/1: ARM: Move the outer_cache definitions into a separate file (1/4)Catalin Marinas2010-03-252-37/+62
| | | | | | | | | | | | | | | | | | To avoid #include collisions with subsequent patches in the series, this patch moves the outer_cache definitions to a separate asm/outercache.h file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'merge' of git://git.secretlab.ca/git/linux-2.6Linus Torvalds2010-04-031-0/+2
|\ \ | | | | | | | | | | | | | | | | | | * 'merge' of git://git.secretlab.ca/git/linux-2.6: powerpc/5200: in lpbfifo, flag DMA irqs as enabled after requesting them powerpc/fsl: add device tree binding for QE firmware of/flattree: Fix unhandled OF_DT_NOP tag when unflattening the device tree
| * | powerpc/5200: in lpbfifo, flag DMA irqs as enabled after requesting themRoman Fietze2010-03-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch avoids unbalanced enable/disable messages for the DMA interrupts when running the 5200 platform SCLPC/BestComm driver in DMA mode. Signed-off-by: Roman Fietze <roman.fietze@telemotive.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* | | Merge branch 'sh/for-2.6.34' of ↵Linus Torvalds2010-04-0211-83/+294
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6 * 'sh/for-2.6.34' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: sh: Fix up the SH-3 build for recent TLB changes. sh: export return_address() symbol. sh: Enable the mmu in start_secondary() sh: Fix FDPIC binary loader arch/sh/kernel: Use set_cpus_allowed_ptr sh: Update ecovec_defconfig USB gadget r8a66597-udc.c: duplicated include sh: update the TLB replacement counter for entry wiring.
| * | | sh: Fix up the SH-3 build for recent TLB changes.Paul Mundt2010-04-024-28/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the MMUCR.URB and ITLB/UTLB differentiation works fine for all SH-4 and later TLBs, these features are absent on SH-3. This splits out local_flush_tlb_all() in to SH-4 and PTEAEX copies while restoring the old SH-3 one, subsequently fixing up the build. This will probably want some further reordering and tidying in the future, but that's out of scope at present. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | sh: export return_address() symbol.Paul Mundt2010-04-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed with some of the tracing code built as modules, so provide the export. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | sh: Enable the mmu in start_secondary()Matt Fleming2010-03-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the boot, enable_mmu() is called from setup_arch() but we don't call setup_arch() for any of the other cpus. So turn on the non-boot cpu's mmu inside of start_secondary(). I noticed this bug on an SMP board when trying to map I/O memory (smsc911x registers) into the kernel address space. Since the Address Translation bit in MMUCR wasn't set, accessing the virtual address where the smsc911x registers were supposedly mapped actually performed a physical address access. Signed-off-by: Matt Fleming <matt@console-pimps.org> Cc: stable@kernel.org Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | sh: Fix FDPIC binary loaderAndrew Stubbs2010-03-291-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure that the aux table is properly initialized, even when optional features are missing. Without this, the FDPIC loader did not work. Signed-off-by: Andrew Stubbs <ams@codesourcery.com> Cc: stable@kernel.org Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | arch/sh/kernel: Use set_cpus_allowed_ptrJulia Lawall2010-03-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use set_cpus_allowed_ptr rather than set_cpus_allowed. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression E1,E2; @@ - set_cpus_allowed(E1, cpumask_of_cpu(E2)) + set_cpus_allowed_ptr(E1, cpumask_of(E2)) @@ expression E; identifier I; @@ - set_cpus_allowed(E, I) + set_cpus_allowed_ptr(E, &I) // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | sh: Update ecovec_defconfigYusuke Goda2010-03-291-46/+190
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * | | sh: update the TLB replacement counter for entry wiring.Matt Fleming2010-03-262-5/+19
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | Presently the TLB wiring code depends on MMUCR.URB for working out where to place the wired entry, but fails to take the replacment counter in to consideration. This fixes up the wiring logic and ensures that wired entries remain so. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* | | microblaze: Support word copying in copy_tofrom_userMichal Simek2010-04-011-14/+25
| | | | | | | | | | | | | | | | | | | | | | | | Word copying is used only for aligned addresses. Here is space for improving to use any better copying technique. Look at memcpy implementation. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Print early printk information to log bufferMichal Simek2010-04-011-9/+15
| | | | | | | | | | | | | | | | | | | | | If early printk console is not enabled then all messages are written to log buffer. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: head.S typo fixMichal Simek2010-04-011-2/+2
| | | | | | | | | | | | | | | | | | I forget to change register name in comments. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Use MICROBLAZE_TLB_SIZE in asm codeMichal Simek2010-04-012-3/+3
| | | | | | | | | | | | | | | | | | | | | TLB size was hardcoded in asm code. This patch brings ability to change TLB size only in one place. (mmu.h). Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Kconfig Fix - pciMichal Simek2010-04-011-3/+0
| | | | | | | | | | | | | | | | | | I forget to remove pci Kconfig option. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Adding likely macrosMichal Simek2010-04-016-26/+28
| | | | | | | | | | | | | | | | | | | | | On the base on GCOV analytics is helpful to add likely/unlikely macros. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Add .type and .size to ASM functionsMichal Simek2010-04-013-1/+22
| | | | | | | | | | | | | | | | | | Cachegrind analysis need this fix to be able to log asm functions. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Fix TLB macrosMichal Simek2010-04-011-1/+2
| | | | | | | | | | | | | | | | | | To be able to do trace TLB operations. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Use instruction with delay slotMichal Simek2010-04-011-8/+5
| | | | | | | | | | | | | | | | | | Sync labels. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Remove additional resr and rear loadingMichal Simek2010-04-011-15/+3
| | | | | | | | | | | | | | | | | | RESR and REAR uses the same regs in whole file. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Change register usage for ESR and EARMichal Simek2010-04-011-35/+35
| | | | | | | | | | | | | | | | | | | | | | | | This change synchronize register usage in code. ESR = R4 EAR = R3 Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Prepare work for optimization in exception codeMichal Simek2010-04-011-6/+3
| | | | | | | | | | | | | | | | | | Any sync branch must follow mts instructions not mfs. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Add DEBUG optionMichal Simek2010-04-011-0/+2
| | | | | | | | | | | | | | | | | | Disable debug option in asm code. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Support systems without lmb bramMichal Simek2010-04-011-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the system has no lmb bram, main memory should be start from zero because of microblaze vectors. DTS fragment could look like: DDR2_SDRAM: memory@0 { device_type = "memory"; reg = < 0x0 0x10000000 >; } ; Then you have to setup CONFIG_KERNEL_BASE_ADDR=0 which caused that kernel physical start address will be zero. On reset vector place will be jump to 0x100 and on 0x100 starts kernel text. You have to solve how to load the kernel before cpu starts. Tested with XMD. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: Sync strlen, strnlen, copy_to/from_userMichal Simek2010-04-011-56/+32
| | | | | | | | | | | | | | | | | | Last sync. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: Unify __copy_tofrom_userMichal Simek2010-04-012-39/+22
| | | | | | | | | | | | | | | | | | Move to generic location. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: Move functions to generic locationMichal Simek2010-04-013-200/+61
| | | | | | | | | | | | | | | | | | noMMU and MMU use them. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: Fix put_user for noMMUMichal Simek2010-04-011-22/+56
| | | | | | | | | | | | | | | | | | | | | | | | Here is small regression on dhrystone tests and I think that on all benchmarking tests. It is due to better checking mechanism in put_user macro Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: Fix get_user macro for noMMUMichal Simek2010-04-011-23/+66
| | | | | | | | | | | | | | | | | | Use unified version. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: fix clear_user for noMMU kernelMichal Simek2010-04-011-45/+36
| | | | | | | | | | | | | | | | | | | | | Previous patches fixed only MMU version and this is the first patch for noMMU kernel Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: Fix strncpy_from_user functionMichal Simek2010-04-011-3/+11
| | | | | | | | | | | | | | | | | | Generic implementation for noMMU and MMU version Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: fix copy_from_user macroMichal Simek2010-04-011-9/+14
| | | | | | | | | | | | | | | | | | copy_from_user macro also use copy_tofrom_user function Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: copy_to_user unificationMichal Simek2010-04-011-9/+16
| | | | | | | | | | | | | | | | | | | | | noMMU and MMU kernel will use copy copy_tofrom_user asm implementation. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: sync put/get/clear_user macrosMichal Simek2010-04-011-37/+69
| | | | | | | | | | | | | | | | | | Add macro description and resort. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: fix put_user and get_user macrosMichal Simek2010-04-011-51/+49
| | | | | | | | | | | | | | | | | | Use FIXUP macros and resort them. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: fix __get_user_asm macroMichal Simek2010-04-011-16/+17
| | | | | | | | | | | | | | | | | | It is used __FIXUP_SECTION and __EX_TABLE_SECTION macros. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: uaccess: fix clean user macroMichal Simek2010-04-011-34/+55
| | | | | | | | | | | | | | | | | | | | | | | | This is the first patch which does uaccess unification. I choosed to do several patches to be able to use bisect in future if any fault happens. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: move noMMU __range_ok function to uaccess.hMichal Simek2010-04-012-9/+6
| | | | | | | | | | | | | | | | | | | | | The same noMMU and MMU functions should be placed in one file. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Move exception_table_entry upwardMichal Simek2010-04-011-16/+15
| | | | | | | | | | | | | | | | | | Just sort to be able remove whole block. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | | microblaze: Remove segment.hMichal Simek2010-04-015-52/+34
| | | | | | | | | | | | | | | | | | | | | I would like to use asm-generic uaccess.h where are segment macros defined. This is just first step. Signed-off-by: Michal Simek <monstr@monstr.eu>
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