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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Kevin Hilman:
"These are changes that arrived a little late before the merge window,
or had dependencies on previous branches.
Highlights:
- ux500: misc. cleanup, fixup I2C devices
- exynos: DT updates for RTC; PM updates
- at91: DT updates for NAND; new platforms added to generic defconfig
- sunxi: DT updates: cubieboard2, pinctrl driver, gated clocks
- highbank: LPAE fixes, select necessary ARM errata
- omap: PM fixes and improvements; OMAP5 mailbox support
- omap: basic support for new DRA7xx SoCs"
* tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
ARM: dts: vexpress: Add CCI node to TC2 device-tree
ARM: EXYNOS: Skip C1 cpuidle state for exynos5440
ARM: EXYNOS: always enable PM domains support for EXYNOS4X12
ARM: highbank: clean-up some unused includes
ARM: sun7i: Enable the A20 clocks in the DTSI
ARM: sun6i: Enable clock support in the DTSI
ARM: sun5i: dt: Use the A10s gates in the DTSI
ARM: at91: at91_dt_defconfig: enable rm9200 support
ARM: dts: add ADC device tree node for exynos5420/5250
ARM: dts: Add RTC DT node to Exynos5420 SoC
ARM: dts: Update the "status" property of RTC DT node for Exynos5250 SoC
ARM: dts: Fix the RTC DT node name for Exynos5250
irqchip: mmp: avoid to include irqs head file
ARM: mmp: avoid to include head file in mach-mmp
irqchip: mmp: support irqchip
irqchip: move mmp irq driver
ARM: OMAP: AM33xx: clock: Add RNG clock data
ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX
ARM: OMAP4: clock: Lock PLLs in the right sequence
ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS
...
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The Versatile Express V2P-CA15_A7 (aka TC2) has a CCI-400 which is
needed to get Multi-Cluster Power Management (MCPM) working.
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into late/all
From Tony Lindgren:
Add basic support for devices on dra7xx by adding the PRCM and hwmod
parts the same way as for other omaps. This is still needed in
addition to device tree support for things like power management.
Via Paul Walmsley <paul@pwsan.com>:
This series adds basic TI DRA7xx PRCM and hwmod support.
Basic test logs are available here:
http://www.pwsan.com/omap/testlogs/dra7xx_prcm_devel_v3.12/20130823050445/
Note that DRA7xx could not be tested locally, since I don't have a board.
* tag 'omap-for-v3.12/dra7xx-prcm' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP: DRA7: Enable PM framework initializations
ARM: OMAP: DRA7: hwmod: Create initial DRA7XX SoC data
ARM: OMAP: DRA7: Reuse the omap44xx_restart and fix the device instance
ARM: OMAP: DRA7: powerdomain: Handle missing vc/vp
ARM: OMAP: DRA7: powerdomain: Add DRA7XX data and update header
ARM: OMAP: DRA7: clockdomain: Add DRA7XX data and update header
ARM: OMAP: DRA7: PRCM: Add DRA7XX local MPU PRCM regsiters
ARM: OMAP: DRA7: CM: Add minimal regbit shifts
ARM: OMAP: DRA7: CM: Add DRA7XX register defines
ARM: OMAP: DRA7: PRM: Add DRA7XX register definitions
ARM: DRA7: Add the build support in omap2plus
ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5
ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'
ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512
ARM: DRA7: board-generic: Add basic DT support
ARM: DRA7: Resue the clocksource, clockevent support
ARM: DRA7: Reuse io tables and add a new .init_early
ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra
Signed-off-by: Olof Johansson <olof@lixom.net>
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Initialise powerdomains, clockdomains, and hwmod frameworks.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Adding the hwmod data for DRA7XX platforms.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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The omap44xx_restart used on omap4 and omap5 devices can be reused
on dra7 devices as well. The device instance however is different
across omap5 and dra7 as compared to omap4. So fix this for omap5
as well as dra7.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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DRA7 belongs to the omap4plus devices which reuse the omap4_pwrdm_operations
ops for powerdomain control. DRA7 however has no VC/VP while all the
earlier omap4plus devices did.
So use the .pwrdm_has_voltdm() ops to pass this info on to the core.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Add the data file to describe all power domains inside the DRA7XX SoC.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: added generation notation to comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Add the data file to describe all clock domains inside the DRA7XX SoC
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: added generation notation to comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Add the PRCM MPU registers for DRA7XX platforms
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: added generation notation to comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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This header contains minimal regbits that are currently used in code.
This header has traditionally been autogenerated on OMAP4+ devices but
the autogenerated contents are largely (95%) unused and hence to reduce
unsued data in the kernel this header has been cut down (from the autogen
output) to whatever is currently needed. This is done by running a cleanup
script on top of the existing autogen script.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Ambresh K <ambresh@ti.com>
[paul@pwsan.com: added generation notation in the comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Add the new defines for DRA7XX CM registers.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: added generation notation in comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Add the new defines for DRA7xx prm module registers.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: added generation notation in the comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into late/all
From Tony Lindgren:
OMAP PRCM and hwmod fixes and improvments via Paul Walmsley <paul@pwsan.com>:
Various OMAP PRCM & hwmod fixes and improvements. Notable changes
include:
- a fix for OMAP4 PLL locking to avoid a bootloader dependency that
causes nasty log spew on startup
- AM33xx DEBUGSS support fixes in hwmod data
- OMAP5 mailbox support in hwmod data
Basic test logs are here:
http://www.pwsan.com/omap/testlogs/prcm_a_for_v3.12/20130823125002/
Note that the 3530 failure is due to the mysterious transient serial
issue affecting 3530 for several releases now, which causes a log
parsing failure. PM still seems to work.
* tag 'omap-for-v3.12/prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP: AM33xx: clock: Add RNG clock data
ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX
ARM: OMAP4: clock: Lock PLLs in the right sequence
ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS
ARM: OMAP2+: Only write the sysconfig on idle when necessary
ARM: OMAP5: hwmod data: Add mailbox data
Signed-off-by: Olof Johansson <olof@lixom.net>
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'am33xx_devel_v3.12' into prcm_a_for_v3.12
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Add clock data for RNG module on AM33xx SoC.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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In the original hwmod data file, DebugSS entry was disabled,
since we didn't (and do not) have SW to control it.
This patch enables it back with right data, so that it can be
controlled by different ways; and the suggested method it to
have modular driver for debugSS as well.
Refer to the link for more discussion on handling of debugSS -
https://patchwork.kernel.org/patch/2212111/
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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This patch adds alwon powerdomain support for TI81XX, which is required
for stable functioning of a big number of TI81XX subsystems.
Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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On OMAP4 we have clk_set_rate()s being done for a few
DPLL clock nodes, as part of the clock init code, since
the bootloaders no longer locks these DPLLs.
So we have a clk_set_rate() done for a ABE DPLL node (which
inturn locks it) followed by a clk_set_rate() for the USB DPLL.
With USB DPLL being in bypass, we have this parent->child
relationship thats formed while the clocks get registered.
dpll_abe_ck
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V
dpll_abe_x2_ck
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V
dpll_abe_m3x2_ck
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V
usb_hs_clk_div_ck
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V
dpll_usb_ck
This is because usb_hs_clk_div_ck is bypass clock for dpll_usb_ck.
So with this parent->child relationship in place, a clk_set_rate()
on ABE DPLL results eventually in a clk_set_rate() call on USB DPLL,
because CCF does a clk_change_rate() (as part of clk_set_rate()) on
all downstream clocks resulting from a rate change on the top clock.
So its important that we lock USB DPLL before we lock ABE DPLL.
Without which we see these error logs at boot.
[These error logs will not be seen if using a bootloader that locks
USB DPLL]
[ 0.000000] clock: dpll_usb_ck failed transition to 'locked'
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7
[ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
[ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
[ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
[ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7
[ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
[ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
[ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
[ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7
[ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
[ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
[ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
[ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7
[ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
[ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
[ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
[ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7
[ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
[ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
[ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
[ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7
[ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
[ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
[ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
[ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
[ 0.000000] clock: trace_clk_div_ck: could not find divisor for target rate 0 for parent pmd_trace_clk_mux_ck
[ 0.000000] Division by zero in kernel.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Currently, whenever we idle a device _idle_sysc() is called and writes to the
devices SYSCONFIG register to set the idle mode. A lot devices are using the
smart-idle mode and so the write to the SYSCONFIG register is programming the
same value that is already stored in the register.
Writes to the devices SYSCONFIG register can be slow, for example, writing to
the DMTIMER SYSCONFIG register takes 3 interface clock cycles and 3 functional
clock cycles. If the DMTIMER is using the slow 32kHz functional clock this can
take ~100us.
Furthermore, during boot on an OMAP4430 panda board, I see that there are 100
calls to _idle_sysc(), however, only 3 out of the 100 calls actually write
the SYSCONFIG register with a new value.
Therefore, to avoid unnecessary writes to device SYSCONFIG registers when
idling the device, only write the value if the value has changed. It should be
safe to do this on idle as the context of the register will never be lost while
the device is active.
Verified that suspend, CORE off and retention states are working with this
change on OMAP3430 Beagle board.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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Add the hwmod data for the mailbox IP in OMAP5 SoC.
This is needed to be able to enable the OMAP mailbox
support for OMAP5.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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late/all
From Rob Herring:
Updates for Highbank for 3.12:
- A couple of fixes to enable LPAE.
- pl08x driver fixes to make it build with ARCH_DMA_ADDR_T_64BIT.
- Avoid L2 related smc calls on Midway.
- Add selecting of necesssary ARM errata.
* tag 'highbank-for-3.12' of git://sources.calxeda.com/kernel/linux:
ARM: highbank: clean-up some unused includes
ARM: highbank: avoid L2 cache smc calls when PL310 is not present
ARM: move outer_cache declaration out of ifdef
ARM: highbank: select ARCH_DMA_ADDR_T_64BIT for LPAE
DMA: fix printk warning in AMBA PL08x DMA driver
DMA: fix AMBA PL08x compilation issue with 64bit DMA address type
ARM: highbank: select required errata work-arounds
ARM: highbank: select ARCH_HAS_HOLES_MEMORYMODEL
ARM: highbank: enable DMA zone for LPAE
ARM: use phys_addr_t for DMA zone sizes
Signed-off-by: Olof Johansson <olof@lixom.net>
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Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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While Midway firmware handles L2 smc calls as nops, the custom smc calls
present a problem when running virtualized Midway guest. They aren't
needed so just avoid calling them.
In the process, cleanup the L2X0 ifdefs and use IS_ENABLED instead.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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Move the outer_cache declaration of the CONFIG_OUTER_CACHE ifdef so that
outer_cache can be used inside IS_ENABLED condition.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
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ECX-2000 has some 64-bit capable DMA and therefore needs dma_addr_t
to be a 64-bit size.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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Ensure necessary errata work-arounds are always enabled for Highbank
and Midway platforms. Highbank requires 764369 and 764369. Midway requires
798181, but only the first half of the work-around (no IPI). Support for
skipping the IPI is introduced in another commit.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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On Midway, the first 4G of memory starts at 0 and the rest of memory
(4GB+) starts at 0x2_00000000, so we need to enable pfn_valid checks
by selecting ARCH_HAS_HOLES_MEMORYMODEL.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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Some devices are restricted to 32-bit DMA. Thus the platform dma_zone_size
needs to be set. Otherwise dma-mapping code is complaining, e.g.
calxedaxgmac fff50000.ethernet: coherent DMA mask 0xffffffff is smaller
than system GFP_DMA mask 0xffffffffffffffff
Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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In order to specify a DMA zone size of 4GB on LPAE systems, the sizes need
to be 64-bit. So make machine_desc.dma_zone_size and arm_dma_zone_size be
phys_addr_t instead of unsigned long.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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From Nicolas Ferre:
AT91 SoC update for 3.12 take 1
- enable kernel uncompress information output for
SoC where it was missing: at91sam9n12 and sama5d3
- addition of at91rm9200 to the generic at91_dt_defconfig
* tag 'at91-soc' of git://github.com/at91linux/linux-at91:
ARM: at91: at91_dt_defconfig: enable rm9200 support
ARM: at91: sam9n12: enable kernel uncompress info output
ARM: at91: sama5: enable kernel uncompress info output
ARM: at91: include sama5d3.h into hardware.h
ARM: at91: sama5d3: add definition for usart base address
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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The sam9n12 use the same array usart as sam9x5, add it which will
enable output kernel uncompress info:
---8>---
Uncompressing Linux... done, booting the kernel.
---<8---
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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Enable kernel uncompress info output, which will show as following:
---8>---
Uncompressing Linux... done, booting the kernel.
---<8---
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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late/all
From Maxime Ripard:
Allwinner DT changes for 3.12, take 3 and 4
These patches add support for:
- The cubieboard2 board
- The pinctrl driver that got merged for the A20 and A31
- The associated muxing for the A20 and A31 boards already supported
- Enables the gated clocks on the A10s, A20 and A31 DTSI.
* tag 'sunxi-dt-for-3.12-4' of https://github.com/mripard/linux:
ARM: sun7i: Enable the A20 clocks in the DTSI
ARM: sun6i: Enable clock support in the DTSI
ARM: sun5i: dt: Use the A10s gates in the DTSI
ARM: sun7i: Add Cubieboard2 Device Tree
ARM: sun7i: a20-olinuxino: Enable the user LED
ARM: sun7i: a20-olinuxino: Enable UARTs muxing
ARM: sun7i: DT: Add UART muxing options to the DTSI
ARM: sun7i: Add the PIO controller node to the DTSI
ARM: sun6i: colombus: Add uart0 muxing
ARM: sun6i: Add UART0 muxing options
ARM: sunxi: dt: Add PIO controller to A31 DTSI
Signed-off-by: Olof Johansson <olof@lixom.net>
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Now that the clock driver knows about the available clocks found on the
A20, we can build up the clock tree from the device tree.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Now that the clock driver has support for the A31 clocks, we can add
them to the DTSI and start using them in the relevant hardware blocks.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The A10s has only a subset of the A10 gates. Now that the clock driver
has support for this gates set, switch to it in the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
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The Cubieboard2 is the successor of the first Cubieboard, and shares the
same hardware, except that the Allwinner A10 found initially has been
replaced by an Allwinner A20.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The A20-olinuxino Micro has a LED connected to the PH2 pin. Use the
gpio-led driver to enable the control over this LED.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Instead of relying on the bootloader to mux the UART pins properly, do
it on our own and register the rightful pins for the A20-olinuxino in
the DT using pinctrl.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The UARTs on the A20 can be muxed to several pins. Add a few options to
the DTSI so that we can start using them in the boards' DT.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The PIO controller is responsible for the GPIO/muxing/external
interrupts handling. Now that we have support for the A20 pin set in the
pinctrl driver, we can start using it in the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The A31 has a different set of pins than the one found on the A10 and
A13. Now that we have support for the A31 pin set in the pinctrl driver,
we can enable it in the DTSI with its own compatible.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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From Nicolas Ferre:
AT91 DT changes for 3.12, take 2
- addition of the Nand Flash Controller (NFC) in DT
for sama5d3 SoC. This NFC will enhance the traditional
Nand Flash handling (SMC + PMECC).
* tag 'at91-dt' of git://github.com/at91linux/linux-at91:
ARM: at91/dt: sama5d3xek: reduce the ROM code mapping for pmecc lookup table
ARM: at91/dt: sama5d3xek: Enable NFC support in dts
ARM: at91/dt: sama5d3xek: remove the useless NFC dt parameters
ARM: at91/dt: sam9x5ek: add sound configuration
ARM: at91/dt: sam9x5ek: enable SSC
ARM: at91/dt: sam9x5ek: add WM8731 codec
ARM: at91/dt: sam9x5: add SSC DMA parameters
ARM: at91/dt: add at91rm9200 PQFP package version
ARM: at91: at91rm9200: set default mmc0 pinctrl-names
ARM: at91: at91sam9n12: correct pin number of gpio-key
ARM: at91: at91sam9n12: add qt1070 support
ARM: at91: at91sam9n12: add pinctrl of TWI
ARM: at91: Add PMU support for sama5d3
ARM: at91: at91sam9260: add missing pinctrl-names on mmc
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Signed-off-by: Josh Wu <josh.wu@atmel.com>
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