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* Merge tag 'clk-for-linus' of ↵Linus Torvalds2018-04-141-2/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The large diff this time around is from the addition of a new clk driver for the TI Davinci family of SoCs. So far those clks have been supported with a custom implementation of the clk API in the arch port instead of in the CCF. With this driver merged we're one step closer to having a single clk API implementation. The other large diff is from the Amlogic clk driver that underwent some major surgery to use regmap. Beyond that, the biggest hitter is Samsung which needed some reworks to properly handle clk provider power domains and a bunch of PLL rate updates. The core framework was fairly quiet this round, just getting some cleanups and small fixes for some of the more esoteric features. And the usual set of driver non-critical fixes, cleanups, and minor additions are here as well. Core: - Rejig clk_ops::init() to be a little earlier for phase/accuracy ops - debugfs ops macroized to shave some lines of boilerplate code - Always calculate the phase instead of caching it in clk_get_phase() - More __must_check on bulk clk APIs New Drivers: - TI's Davinci family of SoCs - Intel's Stratix10 SoC - stm32mp157 SoC - Allwinner H6 CCU - Silicon Labs SI544 clock generator chip - Renesas R-Car M3-N and V3H SoCs - i.MX6SLL SoCs Removed Drivers: - ST-Ericsson AB8540/9540 Updates: - Mediatek MT2701 and MT7622 audsys support and MT2712 updates - STM32F469 DSI and STM32F769 sdmmc2 support - GPIO clks can sleep now - Spreadtrum SC9860 RTC clks - Nvidia Tegra MBIST workarounds and various minor fixes - Rockchip phase handling fixes and a memory leak plugged - Renesas drivers switch to readl/writel from clk_readl/clk_writel - Renesas gained CPU (Z/Z2) and watchdog support - Rockchip rk3328 display clks and rk3399 1.6GHz PLL support - Qualcomm PM8921 PMIC XO buffers - Amlogic migrates to regmap APIs - TI Keystone clk latching support - Allwinner H3 and H5 video clk fixes - Broadcom BCM2835 PLLs needed another bit to enable - i.MX6SX CKO mux fix and i.MX7D Video PLL divider fix - i.MX6UL/ULL epdc_podf support - Hi3798CV200 COMBPHY0 and USB2_OTG_UTMI and phase support for eMMC" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (233 commits) clk: davinci: add a reset lookup table for psc0 clk: imx: add clock driver for imx6sll dt-bindings: imx: update clock doc for imx6sll clk: imx: add new gate/gate2 wrapper funtion clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux clk: cs2000: set pm_ops in hibernate-compatible way clk: bcm2835: De-assert/assert PLL reset signal when appropriate clk: imx7d: Move clks_init_on before any clock operations clk: imx7d: Correct ahb clk parent select clk: imx7d: Correct dram pll type clk: imx7d: Add USB clock information clk: socfpga: stratix10: add clock driver for Stratix10 platform dt-bindings: documentation: add clock bindings information for Stratix10 clk: ti: fix flag space conflict with clkctrl clocks clk: uniphier: add additional ethernet clock lines for Pro4 clk: uniphier: add SATA clock control support clk: uniphier: add PCIe clock control support clk: Add driver for the si544 clock generator chip clk: davinci: Remove redundant dev_err calls clk: uniphier: add ethernet clock control support for PXs3 ...
| *-. Merge branches 'clk-stratix10', 'clk-imx', 'clk-bcm', 'clk-cs2000' and ↵Stephen Boyd2018-04-061-0/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-imx6sll' into clk-next * clk-stratix10: clk: socfpga: stratix10: add clock driver for Stratix10 platform dt-bindings: documentation: add clock bindings information for Stratix10 * clk-imx: clk: imx7d: Move clks_init_on before any clock operations clk: imx7d: Correct ahb clk parent select clk: imx7d: Correct dram pll type clk: imx7d: Add USB clock information clk: imx: pllv2: avoid using uninitialized values clk: imx6ull: Add epdc_podf instead of sim_podf clk: imx: imx7d: correct video pll clock tree clk: imx: imx7d: add the Keypad Port module clock clk: imx7d: add CAAM clock clk: imx: imx7d: add the snvs clock clk: imx: imx6sx: update cko mux options * clk-bcm: clk: bcm2835: De-assert/assert PLL reset signal when appropriate * clk-cs2000: clk: cs2000: set pm_ops in hibernate-compatible way * clk-imx6sll: clk: imx: add clock driver for imx6sll dt-bindings: imx: update clock doc for imx6sll clk: imx: add new gate/gate2 wrapper funtion clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux
| | * | clk: socfpga: stratix10: add clock driver for Stratix10 platformDinh Nguyen2018-04-061-0/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | Add a clock driver for the Stratix10 SoC. The driver is similar to the Cyclone5/Arria10 platforms, with the exception that this driver only uses one single clock binding. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| *---. | Merge branches 'clk-davinci', 'clk-si544', 'clk-rockchip', 'clk-uniphier' ↵Stephen Boyd2018-04-061-0/+2
| |\ \ \| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and 'clk-ti-flag-fix' into clk-next * clk-davinci: clk: davinci: Remove redundant dev_err calls clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks clk: davinci: New driver for TI DA8XX CFGCHIP clocks dt-bindings: clock: Add bindings for DA8XX CFGCHIP clocks clk: davinci: Add platform information for TI DM646x PSC clk: davinci: Add platform information for TI DM644x PSC clk: davinci: Add platform information for TI DM365 PSC clk: davinci: Add platform information for TI DM355 PSC clk: davinci: Add platform information for TI DA850 PSC clk: davinci: Add platform information for TI DA830 PSC clk: davinci: New driver for davinci PSC clocks dt-bindings: clock: New bindings for TI Davinci PSC clk: davinci: Add platform information for TI DM646x PLL clk: davinci: Add platform information for TI DM644x PLL clk: davinci: Add platform information for TI DM365 PLL clk: davinci: Add platform information for TI DM355 PLL clk: davinci: Add platform information for TI DA850 PLL clk: davinci: Add platform information for TI DA830 PLL clk: davinci: New driver for davinci PLL clocks dt-bindings: clock: Add new bindings for TI Davinci PLL clocks * clk-si544: clk: Add driver for the si544 clock generator chip * clk-rockchip: clk: rockchip: assign correct id for pclk_ddr and hclk_sd in rk3399 clk: rockchip: Fix error return in phase clock registration clk: rockchip: Correct the behaviour of restoring cached phase clk: rockchip: Fix wrong parents for MMC phase clock for rk3328 clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228 clk: rockchip: Add 1.6GHz PLL rate for rk3399 clk: rockchip: Restore the clock phase after the rate was changed clk: rockchip: Prevent calculating mmc phase if clock rate is zero clk: rockchip: Free the memory on the error path clk: rockchip: document hdmi_phy external input for rk3328 clk: rockchip: add flags for rk3328 dclk_lcdc clk: rockchip: remove ignore_unused flag from rk3328 vio_h2p clocks clk: rockchip: protect all remaining rk3328 interconnect clocks clk: rockchip: export sclk_hdmi_sfc on rk3328 clk: rockchip: remove HCLK_VIO from rk3328 dt header clk: rockchip: fix hclk_vio_niu on rk3328 * clk-uniphier: clk: uniphier: add additional ethernet clock lines for Pro4 clk: uniphier: add SATA clock control support clk: uniphier: add PCIe clock control support clk: uniphier: add ethernet clock control support for PXs3 clk: uniphier: add Pro4/Pro5/PXs2 audio system clock * clk-ti-flag-fix: clk: ti: fix flag space conflict with clkctrl clocks clk: ti: clkctrl: add support for CLK_SET_RATE_PARENT flag
| | | * | clk: Add driver for the si544 clock generator chipMike Looijmans2018-03-231-0/+1
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the driver and devicetree documentation for the Silicon Labs SI544 clock generator chip. This is an I2C controlled oscillator capable of generating clock signals ranging from 200kHz to 1500MHz. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> [sboyd: assign max_freq to 0 in is_valid_frequency() to squelch warning] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * / clk: davinci: New driver for davinci PLL clocksDavid Lechner2018-03-201-0/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a new driver for mach-davinci PLL clocks. This is porting the code from arch/arm/mach-davinci/clock.c to the common clock framework. Additionally, it adds device tree support for these clocks. The ifeq ($(CONFIG_COMMON_CLK), y) in the Makefile is needed to prevent compile errors until the clock code in arch/arm/mach-davinci is removed. Note: although there are similar clocks for TI Keystone we are not able to share the code for a few reasons. The keystone clocks are device tree only and use legacy one-node-per-clock bindings. Also the register layouts are a bit different, which would add even more if/else mess to the keystone clocks. And the keystone PLL driver doesn't support setting clock rates. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | clk: stm32: add configuration flags for each of the stm32 driversBenjamin Gaignard2018-03-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add two configuration flags to be able to not compile all the time stm32f and stm32h7 drivers when ARCH_STM32 is set. That help to save some space on those small platforms. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | clk: stm32mp1: Introduce STM32MP1 clock driverGabriel Fernandez2018-03-111-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | This patch introduces the mechanism to probe stm32mp1 driver. It also defines registers definition. This patch also introduces the generic mechanism to register a clock (a simple gate, divider and fixed factor). All clocks will be defined in one table. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* / clk: add support for clocks provided by SCMISudeep Holla2018-02-281-0/+1
|/ | | | | | | | | | | | | | | | On some ARM based systems, a separate Cortex-M based System Control Processor(SCP) provides the overall power, clock, reset and system control. System Control and Management Interface(SCMI) Message Protocol is defined for the communication between the Application Cores(AP) and the SCP. This patch adds support for the clocks provided by SCP using SCMI protocol. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
*---. Merge branches 'clk-aspeed', 'clk-lock-UP', 'clk-mediatek' and ↵Stephen Boyd2018-01-271-1/+2
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-allwinner' into clk-next * clk-aspeed: clk: aspeed: Handle inverse polarity of USB port 1 clock gate clk: aspeed: Fix return value check in aspeed_cc_init() clk: aspeed: Add reset controller clk: aspeed: Register gated clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register core clocks clk: Add clock driver for ASPEED BMC SoCs dt-bindings: clock: Add ASPEED constants * clk-lock-UP: clk: fix reentrancy of clk_enable() on UP systems * clk-mediatek: clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being built clk: mediatek: Fix all warnings for missing struct clk_onecell_data clk: mediatek: fixup test-building of MediaTek clock drivers clk: mediatek: group drivers under indpendent menu * clk-allwinner: clk: sunxi-ng: a83t: Add M divider to TCON1 clock clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU clk: sunxi-ng: add support for Allwinner H3 DE2 CCU dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3 clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL clk: sunxi-ng: Support fixed post-dividers on NM style clocks clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: Support fixed post-dividers on MP style clocks clk: sunxi: Use PTR_ERR_OR_ZERO()
| | | * clk: mediatek: fixup test-building of MediaTek clock driversSean Wang2017-12-221-1/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | Let the build system looking into the directiory where the clock drivers resides for the COMPILE_TEST alternative dependency allows test-building the drivers. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * / clk: Add clock driver for ASPEED BMC SoCsJoel Stanley2018-01-271-0/+1
| |/ | | | | | | | | | | | | | | | | | | This adds the stub of a driver for the ASPEED SoCs. The clocks are defined and the static registration is set up. Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* / clk: sprd: Add common infrastructureChunyan Zhang2017-12-221-0/+1
|/ | | | | | | | Added Spreadtrum's clock driver framework together with common structures and interface functions. Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: mb86s7x: Drop non-building driverAndreas Färber2017-09-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It fails to build once we introduce the ARCH_MB86S7X Kconfig symbol: drivers/clk/clk-mb86s7x.c:27:10: fatal error: soc/mb86s7x/scb_mhu.h: No such file or directory #include <soc/mb86s7x/scb_mhu.h> ^~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. And when commenting out that line, we get: drivers/clk/clk-mb86s7x.c: In function 'crg_gate_control': drivers/clk/clk-mb86s7x.c:72:8: error: implicit declaration of function 'mb86s7x_send_packet' [-Werror=implicit-function-declaration] ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ, ^~~~~~~~~~~~~~~~~~~ drivers/clk/clk-mb86s7x.c:72:28: error: 'CMD_PERI_CLOCK_GATE_SET_REQ' undeclared (first use in this function) ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ, ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/clk-mb86s7x.c:72:28: note: each undeclared identifier is reported only once for each function it appears in drivers/clk/clk-mb86s7x.c: In function 'crg_rate_control': drivers/clk/clk-mb86s7x.c:116:10: error: 'CMD_PERI_CLOCK_RATE_SET_REQ' undeclared (first use in this function) code = CMD_PERI_CLOCK_RATE_SET_REQ; ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/clk-mb86s7x.c:121:10: error: 'CMD_PERI_CLOCK_RATE_GET_REQ' undeclared (first use in this function); did you mean 'CMD_PERI_CLOCK_RATE_SET_REQ'? code = CMD_PERI_CLOCK_RATE_GET_REQ; ^~~~~~~~~~~~~~~~~~~~~~~~~~~ CMD_PERI_CLOCK_RATE_SET_REQ drivers/clk/clk-mb86s7x.c: In function 'mhu_cluster_rate': drivers/clk/clk-mb86s7x.c:276:10: error: 'CMD_CPU_CLOCK_RATE_GET_REQ' undeclared (first use in this function) code = CMD_CPU_CLOCK_RATE_GET_REQ; ^~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/clk-mb86s7x.c:278:10: error: 'CMD_CPU_CLOCK_RATE_SET_REQ' undeclared (first use in this function); did you mean 'CMD_CPU_CLOCK_RATE_GET_REQ'? code = CMD_CPU_CLOCK_RATE_SET_REQ; ^~~~~~~~~~~~~~~~~~~~~~~~~~ CMD_CPU_CLOCK_RATE_GET_REQ cc1: some warnings being treated as errors scripts/Makefile.build:302: recipe for target 'drivers/clk/clk-mb86s7x.o' failed make[2]: *** [drivers/clk/clk-mb86s7x.o] Error 1 Remove the driver for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: stm32h7: Add stm32h743 clock driverGabriel Fernandez2017-09-011-0/+1
| | | | | | | | | | | | | This patch enables clocks for STM32H743 boards. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> for MFD changes: Acked-by: Lee Jones <lee.jones@linaro.org> for DT-Bindings Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* ARC: clk: introduce HSDK pll driverEugeniy Paltsev2017-08-311-0/+1
| | | | | | | | | | | | | | | | | | | | | | | HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi. By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2017-07-151-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "Boston platform support: - Document DT bindings - Add CLK driver for board clocks CM: - Avoid per-core locking with CM3 & higher - WARN on attempt to lock invalid VP, not BUG CPS: - Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6 - Prevent multi-core with dcache aliasing - Handle cores not powering down more gracefully - Handle spurious VP starts more gracefully DSP: - Add lwx & lhx missaligned access support eBPF: - Add MIPS support along with many supporting change to add the required infrastructure Generic arch code: - Misc sysmips MIPS_ATOMIC_SET fixes - Drop duplicate HAVE_SYSCALL_TRACEPOINTS - Negate error syscall return in trace - Correct forced syscall errors - Traced negative syscalls should return -ENOSYS - Allow samples/bpf/tracex5 to access syscall arguments for sane traces - Cleanup from old Kconfig options in defconfigs - Fix PREF instruction usage by memcpy for MIPS R6 - Fix various special cases in the FPU eulation - Fix some special cases in MIPS16e2 support - Fix MIPS I ISA /proc/cpuinfo reporting - Sort MIPS Kconfig alphabetically - Fix minimum alignment requirement of IRQ stack as required by ABI / GCC - Fix special cases in the module loader - Perform post-DMA cache flushes on systems with MAARs - Probe the I6500 CPU - Cleanup cmpxchg and add support for 1 and 2 byte operations - Use queued read/write locks (qrwlock) - Use queued spinlocks (qspinlock) - Add CPU shared FTLB feature detection - Handle tlbex-tlbp race condition - Allow storing pgd in C0_CONTEXT for MIPSr6 - Use current_cpu_type() in m4kc_tlbp_war() - Support Boston in the generic kernel Generic platform: - yamon-dt: Pull YAMON DT shim code out of SEAD-3 board - yamon-dt: Support > 256MB of RAM - yamon-dt: Use serial* rather than uart* aliases - Abstract FDT fixup application - Set RTC_ALWAYS_BCD to 0 - Add a MAINTAINERS entry core kernel: - qspinlock.c: include linux/prefetch.h Loongson 3: - Add support Perf: - Add I6500 support SEAD-3: - Remove GIC timer from DT - Set interrupt-parent per-device, not at root node - Fix GIC interrupt specifiers SMP: - Skip IPI setup if we only have a single CPU VDSO: - Make comment match reality - Improvements to time code in VDSO" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (86 commits) locking/qspinlock: Include linux/prefetch.h MIPS: Fix MIPS I ISA /proc/cpuinfo reporting MIPS: Fix minimum alignment requirement of IRQ stack MIPS: generic: Support MIPS Boston development boards MIPS: DTS: img: Don't attempt to build-in all .dtb files clk: boston: Add a driver for MIPS Boston board clocks dt-bindings: Document img,boston-clock binding MIPS: Traced negative syscalls should return -ENOSYS MIPS: Correct forced syscall errors MIPS: Negate error syscall return in trace MIPS: Drop duplicate HAVE_SYSCALL_TRACEPOINTS select MIPS16e2: Provide feature overrides for non-MIPS16 systems MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfo MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructions MIPS: MIPS16e2: Identify ASE presence MIPS: VDSO: Fix a mismatch between comment and preprocessor constant MIPS: VDSO: Add implementation of gettimeofday() fallback MIPS: VDSO: Add implementation of clock_gettime() fallback MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse() MIPS: Use current_cpu_type() in m4kc_tlbp_war() ...
| * clk: boston: Add a driver for MIPS Boston board clocksPaul Burton2017-07-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the clocks provided by the MIPS Boston board from Imagination Technologies. 2 clocks are provided - the system clock & the CPU clock - and each is a simple fixed rate clock whose frequency can be determined by reading a register provided by the board. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | clk: Add Gemini SoC clock controllerLinus Walleij2017-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock controller that derive all clocks from a single crystal, using some documented and some undocumented PLLs, half dividers, counters and gates. This is a best attempt to construct a clock driver for the clocks so at least we can gate off unused hardware and driver the PCI bus clock. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [sboyd@codeaurora.org: Fix devm_ioremap_resource() return value checking] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: keystone: Add sci-clk driver supportTero Kristo2017-06-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In K2G, the clock handling is done through firmware executing on a separate core. Linux kernel needs to communicate to the firmware through TI system control interface to access any power management related resources, including clocks. The keystone sci-clk driver does this, by communicating to the firmware through the TI SCI driver. The driver adds support for registering clocks through DT, and basic required clock operations like prepare/get_rate, etc. Signed-off-by: Tero Kristo <t-kristo@ti.com> [sboyd@codeaurora.org: Make ti_sci_init_clocks() static] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge branch 'clk-bulk-get' into clk-nextStephen Boyd2017-06-031-1/+1
|\ \ | | | | | | | | | | | | | | | * clk-bulk-get: clk: add managed version of clk_bulk_get clk: add clk_bulk_get accessories
| * | clk: add clk_bulk_get accessoriesDong Aisheng2017-06-031-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These helper function allows drivers to get several clk consumers in one operation. If any of the clk cannot be acquired then any clks that were got will be put before returning to the caller. This can relieve the driver owners' life who needs to handle many clocks, as well as each clock error reporting. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Mark Brown <broonie@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Anson Huang <anson.huang@nxp.com> Cc: Robin Gong <yibin.gong@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: Octavian Purdila <octavian.purdila@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* / clk: renesas: Rework Kconfig and Makefile logicGeert Uytterhoeven2017-05-241-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The goals are to: - Allow precise control over and automatic selection of which (sub)drivers are used for which SoC (which may change in the future), - Allow adding support for new SoCs easily, - Allow compile-testing of all (sub)drivers, - Keep driver selection logic in the subsystem-specific Kconfig, independent from the architecture-specific Kconfig (i.e. no "select" from arch/arm64/Kconfig.platforms), to avoid dependencies. This is implemented by: - Introducing Kconfig symbols for all drivers and sub-drivers, - Introducing the Kconfig symbol CLK_RENESAS, which is enabled automatically when building for a Renesas ARM platform, and which enables all required drivers without interaction of the user, based on SoC-specific ARCH_* symbols, - Allowing the user to enable any Kconfig symbol manually if COMPILE_TEST is enabled, - Using the new Kconfig symbols instead of the ARCH_* symbols to control compilation in the Makefile, - Always entering drivers/clk/renesas/ during the build. Note that currently not all (sub)drivers are enabled for compile-testing, as they depend on independent fixes in other subsystems. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: hi6220: Add the hi655x's pmic clockDaniel Lezcano2017-04-221-0/+1
| | | | | | | | | | | | The hi655x multi function device is a PMIC providing regulators. The PMIC also provides a clock for the WiFi and the Bluetooth, let's implement this clock in order to add it in the hi655x MFD and allow proper wireless initialization. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> [sboyd@codeaurora.org: Remove clkdev usage] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: Make x86/ conditional on CONFIG_COMMON_CLKPierre-Louis Bossart2017-01-271-0/+2
| | | | | | | | | | Fix Makefile for x86 support, dependency on CONFIG_COMMON_CLK was not explicit Fixes: 701190fd7419 ('clk: x86: add support for Lynxpoint LPSS clocks') Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933Marek Vasut2017-01-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These chips have two clock inputs, XTAL or CLK, which are muxed into single PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip while the 5P49V5923 requires external XTAL. The PLL feeds two fractional dividers. Each fractional divider feeds output mux, which allows selecting between clock from the fractional divider itself or from output mux on output N-1. In case of output mux 0, the output N-1 is instead connected to the output from the mux feeding the PLL. The driver thus far supports only the 5P49V5923 and 5P49V5933, while it should be easily extensible to the whole 5P49V59xx family of chips as they are all pretty similar. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: linux-renesas-soc@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: Loongson1: Refactor Loongson1 clockKelvin Cheung2016-09-231-1/+1
| | | | | | | | | Factor out the common functions into loongson1/clk.c to support both Loongson1B and Loongson1C. And, put the rest into loongson1/clk-loongson1b.c. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: uniphier: add core support code for UniPhier clock driverMasahiro Yamada2016-09-171-0/+1
| | | | | | | | This includes UniPhier clock driver code, except SoC-specific data arrays. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: max77686: Combine Maxim max77686 and max77802 driverLaxman Dewangan2016-08-161-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The clock IP used on the Maxim PMICs max77686 and max77802 are same. The configuration of clock register is also same except the number of clocks. Part of common code utilisation, there is 3 files for these chips clock driver, one for common and two files for driver registration. Combine both drivers into single file and move common code into same common file reduces the 2 files and make max77686 and max77802 clock driver in single fine. This driver does not depends on the parent driver structure. The regmap handle is acquired through regmap APIs for the register access. This combination of driver helps on adding clock driver for different Maxim PMICs which has similar clock IP like MAX77620 and MAX20024. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> CC: Krzysztof Kozlowski <k.kozlowski@samsung.com> CC: Javier Martinez Canillas <javier@dowhile0.org> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: Makefile: re-sort and clean upMichael Turquette2016-07-191-9/+11
| | | | | | Sorting is hard. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* Merge branch 'clk-sunxi-ng' into clk-nextMichael Turquette2016-07-091-0/+1
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| * clk: sunxi-ng: Add common infrastructureMaxime Ripard2016-07-091-0/+1
| | | | | | | | | | | | | | | | | | Start our new clock infrastructure by adding the registration code, common structure and common code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com
* | clk: meson: only build selected platformsMichael Turquette2016-06-231-1/+1
|/ | | | | | | | | | Break the AmLogic clock code up so that only the necessary parts are compiled and linked. The core code is selected by both arm and arm64 builds with COMMON_CLK_AMLOGIC. The individual drivers have their own config options as well. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2016-05-211-1/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "It's the usual big pile of driver updates and additions, but we do have a couple core changes in here as well. Core: - CLK_IS_CRITICAL support has been added. This should allow drivers to properly express that a certain clk should stay on even if their prepare/enable count drops to 0 (and in turn the parents of these clks should stay enabled). - A clk registration API has been added, clk_hw_register(), and an OF clk provider API has been added, of_clk_add_hw_provider(). These APIs have been put in place to further split clk providers from clk consumers, with the goal being to have clk providers never deal with struct clk pointers at all. Conversion of provider drivers is on going. clkdev has also gained support for registering clk_hw pointers directly so we can convert drivers that don't use devicetree. New Drivers: - Marvell ap806 and cp110 system controllers (with clks inside!) - Hisilicon Hi3519 clock and reset controller - Axis ARTPEC-6 clock controllers - Oxford Semiconductor OXNAS clock controllers - AXS10X I2S PLL - Rockchip RK3399 clock and reset controller Updates: - MMC2 and UART2 clks on Samsung Exynos 3250, ACLK on Samsung Exynos 542x SoCs, and some more clk ID exporting for bus frequency scaling - Proper BCM2835 PCM clk support and various other clks - i.MX clk updates for i.MX6SX, i.MX7, and VF610 - Renesas updates for R-Car H3 - Tegra210 got updates for DisplayPort and HDMI 2.0 - Rockchip driver refactorings and fixes due to adding RK3399 support" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (139 commits) clk: fix critical clock locking clk: qcom: mmcc-8996: Remove clocks that should be controlled by RPM clk: ingenic: Allow divider value to be divided clk: sunxi: Add display and TCON0 clocks driver clk: rockchip: drop old_rate calculation on pll rate changes clk: rockchip: simplify GRF handling in pll clocks clk: rockchip: lookup General Register Files in rockchip_clk_init clk: rockchip: fix the rk3399 sdmmc sample / drv name clk: mvebu: new driver for Armada CP110 system controller dt-bindings: arm: add DT binding for Marvell CP110 system controller clk: mvebu: new driver for Armada AP806 system controller clk: hisilicon: add CRG driver for hi3519 soc clk: hisilicon: export some hisilicon APIs to modules reset: hisilicon: add reset controller driver for hisilicon SOCs clk: bcm/kona: Do not use sizeof on pointer type clk: qcom: msm8916: Fix crypto clock flags clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0 clk/axs10x: Add I2S PLL clock driver clk: imx7d: fix ahb clock mux 1 clk: fix comment of devm_clk_hw_register() ...
| * clk/axs10x: Add I2S PLL clock driverJose Abreu2016-05-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARC SDP I2S clock can be programmed using a specific PLL. This patch has the goal of adding a clock driver that programs this PLL. At this moment the rate values are hardcoded in a table but in the future it would be ideal to use a function which determines the PLL values given the desired rate. Signed-off-by: Jose Abreu <joabreu@synopsys.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: Add Oxford Semiconductor OXNAS Standard ClocksNeil Armstrong2016-04-211-0/+1
| | | | | | | | | | | | | | | | | | Add Oxford Semiconductor OXNAS SoC Family Standard Clocks support. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [sboyd@codeaurora.org: Drop NULL/continue check in registration loop] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * Merge branch 'clk-artpec6' into clk-nextStephen Boyd2016-04-161-0/+1
| |\ | | | | | | | | | | | | | | | * clk-artpec6: clk: add artpec-6 clock controller clk: add device tree binding for Artpec-6 clock controller
| | * clk: add artpec-6 clock controllerLars Persson2016-04-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the main clock controller of the Artpec-6 Soc. Signed-off-by: Lars Persson <larper@axis.com> [sboyd@codeaurora.org: Reformatted driver structure and of match] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: unconditionally recurse into clk/mvebu/Thomas Petazzoni2016-04-021-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | The drivers/clk/mvebu directory is only being built when CONFIG_PLAT_ORION=y. As we are going to support additional mvebu platforms in drivers/clk/mvebu, which don't have CONFIG_PLAT_ORION=y, we need to recurse into this directory regardless of the value of CONFIG_PLAT_ORION. Since all files in drivers/clk/mvebu/ are already conditionally compiled depending on various Kconfig options, we can recurse unconditionally into drivers/clk/mvebu without any other change. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* / CLK: microchip: Add Microchip PIC32 clock driver.Purna Chandra Mandal2016-05-131-0/+1
|/ | | | | | | | | | | | | | This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* clk: renesas: move drivers to renesas directorySimon Horman2016-03-031-1/+1
| | | | | | | | | | | | | This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Along with the above mentioned Kconfig changes it seems appropriate to also rename directories that only hold drivers for such SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge branch 'clk-ti' into clk-nextMichael Turquette2016-03-021-1/+1
|\ | | | | | | | | Conflicts: drivers/clk/Kconfig
| * clk: ti: Allow COMPILE_TEST to build selected driversTony Lindgren2016-03-021-1/+1
| | | | | | | | | | | | | | | | The arch independent drivers can be build testeed with COMPILE_TEST. Let's allow that for drivers/clk/ti. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | clk: shmobile: Remove ARCH_SHMOBILE_MULTISimon Horman2016-02-261-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As of 9b5ba0df4ea4 ("ARM: shmobile: Introduce ARCH_RENESAS") all platforms that use Renesas clock drivers now select ARCH_RENESAS. As it is present in drivers/clk/Makefile ARCH_SHMOBILE_MULTI may now be removed. This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: tango4: rename ARCH_TANGOX to ARCH_TANGOMarc Gonzalez2016-01-291-1/+1
|/ | | | | | | | Requested by arm-soc maintainer Kevin Hilman in v9 review. http://article.gmane.org/gmane.linux.ports.arm.kernel/456331 Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge branch 'clk-lpc32xx' into clk-nextMichael Turquette2015-12-241-1/+1
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| * clk: lpc18xx: add NXP specific COMMON_CLK_NXP configuration symbolVladimir Zapolskiy2015-12-241-1/+1
| | | | | | | | | | | | | | | | | | | | The change adds COMMON_CLK_NXP configuration symbol and enables it for NXP LPC18XX architecture, this is needed to reuse drivers/clk/nxp folder for NXP common clock framework drivers other than LPC18XX one. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | Merge branch 'clk-shmobile-for-v4.5' of ↵Michael Turquette2015-12-221-0/+1
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
| * | clk: shmobile: r8a7795: Add new CPG/MSSR driverGeert Uytterhoeven2015-12-081-0/+1
| |/ | | | | | | | | | | | | Add a new R-Car H3 Clock Pulse Generator / Module Standby and Software Reset driver, using the new CPG/MSSR driver core. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 20:48:56 +0100