| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: actions: Add S900 SoC clock support | Manivannan Sadhasivam | 2018-04-06 | 1 | -0/+3 |
| * | clk: actions: Add pll clock support | Manivannan Sadhasivam | 2018-04-06 | 1 | -0/+1 |
| * | clk: actions: Add composite clock support | Manivannan Sadhasivam | 2018-04-06 | 1 | -0/+1 |
| * | clk: actions: Add factor clock support | Manivannan Sadhasivam | 2018-04-06 | 1 | -0/+1 |
| * | clk: actions: Add divider clock support | Manivannan Sadhasivam | 2018-04-06 | 1 | -0/+1 |
| * | clk: actions: Add mux clock support | Manivannan Sadhasivam | 2018-04-06 | 1 | -0/+1 |
| * | clk: actions: Add gate clock support | Manivannan Sadhasivam | 2018-04-06 | 1 | -0/+1 |
| * | clk: actions: Add common clock driver support | Manivannan Sadhasivam | 2018-04-06 | 1 | -0/+3 |
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