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path: root/drivers/clk/at91/sama5d2.c (follow)
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* clk: at91: clk-master: add notifier for dividerClaudiu Beznea2021-10-271-1/+1
* clk: at91: Fix the declaration of the clocksTudor Ambarus2021-02-101-1/+2
* clk: at91: clk-master: re-factor master clockClaudiu Beznea2020-12-191-15/+27
* clk: at91: clk-programmable: add mux_table optionClaudiu Beznea2020-07-241-1/+2
* clk: at91: clk-peripheral: add support for changeable parent rateClaudiu Beznea2020-07-241-2/+3
* clk: at91: clk-generated: add mux_table optionClaudiu Beznea2020-07-241-1/+1
* clk: at91: clk-generated: pass the id of changeable parent at registrationClaudiu Beznea2020-07-241-16/+15
* clk: at91: allow setting all PMC clock parents via DTMichał Mirosław2020-05-271-1/+5
* clk: at91: allow setting PCKx parent via DTMichał Mirosław2020-05-271-1/+3
* clk: at91: optimize pmc data allocationMichał Mirosław2020-05-271-1/+1
* clk: at91: Add peripheral clock for PTCCodrin Ciubotariu2020-05-271-0/+1
* clk: at91: fix possible deadlockAlexandre Belloni2019-12-161-1/+1
* clk: at91: allow 24 Mhz clock as input for PLLEugen Hristev2019-09-181-1/+1
*-. Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and...Stephen Boyd2019-05-071-1/+11
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| | * clk: at91: Mark struct clk_range as constStephen Boyd2019-04-251-1/+1
| | * clk: at91: allow configuring generated PCR layoutAlexandre Belloni2019-04-251-0/+1
| | * clk: at91: allow configuring peripheral PCR layoutAlexandre Belloni2019-04-251-0/+9
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* / clk: at91: fix programmable clock for sama5d2Matthias Wieloch2019-03-181-1/+9
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* Merge branch 'clk-at91' into clk-nextStephen Boyd2019-03-081-1/+2
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| * clk: at91: enable AUDIOPLL as source for PCKx on SAMA5D2Michał Mirosław2019-01-091-1/+2
* | clk: at91: fix masterck nameAlexandre Belloni2019-02-201-2/+2
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* clk: at91: add sama5d2 PMC driverAlexandre Belloni2018-10-171-0/+336