summaryrefslogtreecommitdiffstats
path: root/drivers/clk/at91/sama7g5.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: at91: sama7g5: fix parents of PDMCs' GCLKCodrin Ciubotariu2022-03-081-4/+4
* clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DTTudor Ambarus2022-01-251-1/+7
* clk: at91: sama7g5: set low limit for mck0 at 32KHzClaudiu Beznea2021-10-271-1/+1
* clk: at91: sama7g5: remove prescaler part of master clockClaudiu Beznea2021-10-271-10/+1
* clk: at91: clk-master: add notifier for dividerClaudiu Beznea2021-10-271-1/+1
* clk: at91: clk-sam9x60-pll: add notifier for div part of PLLClaudiu Beznea2021-10-271-2/+11
* clk: at91: sama7g5: add securam's peripheral clockClaudiu Beznea2021-10-271-0/+1
* clk: at91: sama7g5: remove all kernel-doc & kernel-doc warningsRandy Dunlap2021-08-291-7/+7
* clk: at91: Trivial typo fixes in the file sama7g5.cBhaskar Chowdhury2021-03-131-3/+3
* clk: at91: sama7g5: register cpu clockClaudiu Beznea2020-12-191-7/+6
* clk: at91: clk-master: re-factor master clockClaudiu Beznea2020-12-191-2/+11
* clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHzClaudiu Beznea2020-12-191-14/+47
* clk: at91: sama7g5: decrease lower limit for MCK0 rateClaudiu Beznea2020-12-191-1/+1
* clk: at91: sama7g5: remove mck0 from parent list of other clocksClaudiu Beznea2020-12-191-29/+26
* clk: at91: clk-sam9x60-pll: allow runtime changes for pllClaudiu Beznea2020-12-191-17/+50
* clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev2020-12-191-2/+2
* clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DTEugen Hristev2020-12-191-2/+4
* dt-bindings: clock: at91: add sama7g5 pll definesEugen Hristev2020-12-191-3/+3
* clk: at91: sama7g5: fix compilation errorClaudiu Beznea2020-12-191-2/+4
* clk: at91: sama7g5: add clock support for sama7g5Claudiu Beznea2020-07-241-0/+1059