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path:
root
/
drivers
/
clk
/
at91
/
sama7g5.c
(
follow
)
Commit message (
Expand
)
Author
Age
Files
Lines
*
clk: at91: sama7g5: fix parents of PDMCs' GCLK
Codrin Ciubotariu
2022-03-08
1
-4
/
+4
*
clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DT
Tudor Ambarus
2022-01-25
1
-1
/
+7
*
clk: at91: sama7g5: set low limit for mck0 at 32KHz
Claudiu Beznea
2021-10-27
1
-1
/
+1
*
clk: at91: sama7g5: remove prescaler part of master clock
Claudiu Beznea
2021-10-27
1
-10
/
+1
*
clk: at91: clk-master: add notifier for divider
Claudiu Beznea
2021-10-27
1
-1
/
+1
*
clk: at91: clk-sam9x60-pll: add notifier for div part of PLL
Claudiu Beznea
2021-10-27
1
-2
/
+11
*
clk: at91: sama7g5: add securam's peripheral clock
Claudiu Beznea
2021-10-27
1
-0
/
+1
*
clk: at91: sama7g5: remove all kernel-doc & kernel-doc warnings
Randy Dunlap
2021-08-29
1
-7
/
+7
*
clk: at91: Trivial typo fixes in the file sama7g5.c
Bhaskar Chowdhury
2021-03-13
1
-3
/
+3
*
clk: at91: sama7g5: register cpu clock
Claudiu Beznea
2020-12-19
1
-7
/
+6
*
clk: at91: clk-master: re-factor master clock
Claudiu Beznea
2020-12-19
1
-2
/
+11
*
clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
Claudiu Beznea
2020-12-19
1
-14
/
+47
*
clk: at91: sama7g5: decrease lower limit for MCK0 rate
Claudiu Beznea
2020-12-19
1
-1
/
+1
*
clk: at91: sama7g5: remove mck0 from parent list of other clocks
Claudiu Beznea
2020-12-19
1
-29
/
+26
*
clk: at91: clk-sam9x60-pll: allow runtime changes for pll
Claudiu Beznea
2020-12-19
1
-17
/
+50
*
clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
Eugen Hristev
2020-12-19
1
-2
/
+2
*
clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT
Eugen Hristev
2020-12-19
1
-2
/
+4
*
dt-bindings: clock: at91: add sama7g5 pll defines
Eugen Hristev
2020-12-19
1
-3
/
+3
*
clk: at91: sama7g5: fix compilation error
Claudiu Beznea
2020-12-19
1
-2
/
+4
*
clk: at91: sama7g5: add clock support for sama7g5
Claudiu Beznea
2020-07-24
1
-0
/
+1059