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path: root/drivers/clk/clk-aspeed.c (follow)
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*-. Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and 'c...Stephen Boyd2023-08-301-2/+1
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| | * clk: Annotate struct clk_hw_onecell_data with __counted_byKees Cook2023-08-221-2/+1
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* / clk: Explicitly include correct DT includesRob Herring2023-07-191-1/+1
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* clk: aspeed: Add RMII RCLK gates for both AST2500 MACsAndrew Jeffery2019-11-261-1/+26
* clk: aspeed: Move structures to headerJoel Stanley2019-09-071-64/+3
* clk: aspeed: Add SDIO gateJoel Stanley2019-08-071-3/+8
* clk: Aspeed: Setup video engine clockingEddie James2019-04-181-3/+39
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-08-161-1/+1
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| * clk: aspeed: Fix SDCLK nameLei YU2018-07-061-1/+1
* | clk: aspeed: Support HPLL strapping on ast2400Joel Stanley2018-07-111-13/+29
* | clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as criticalJoel Stanley2018-07-061-2/+2
* | clk: aspeed: Treat a gate in reset as disabledBenjamin Herrenschmidt2018-07-061-0/+13
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-06-091-11/+46
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| *-. Merge branches 'clk-imx6sx', 'clk-imx7d-enet' and 'clk-aspeed-24' into clk-nextStephen Boyd2018-06-041-1/+8
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| | | * clk: aspeed: Add 24MHz fixed clockLei YU2018-06-011-1/+8
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| * | clk:aspeed: Fix reset bits for PCI/VGA and PECIJae Hyun Yoo2018-05-161-2/+2
| * | clk: aspeed: Support second reset registerJoel Stanley2018-05-151-8/+36
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* / treewide: Use struct_size() for kmalloc()-familyKees Cook2018-06-061-3/+3
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* clk: aspeed: Prevent reset if clock is enabledEddie James2018-03-151-12/+17
* clk: aspeed: Fix is_enabled for certain clocksEddie James2018-03-151-1/+2
* clk: aspeed: Handle inverse polarity of USB port 1 clock gateBenjamin Herrenschmidt2018-01-271-3/+12
* clk: aspeed: Fix return value check in aspeed_cc_init()Wei Yongjun2018-01-271-1/+1
* clk: aspeed: Add reset controllerJoel Stanley2018-01-271-1/+81
* clk: aspeed: Register gated clocksJoel Stanley2018-01-271-0/+130
* clk: aspeed: Add platform driver and register PLLsJoel Stanley2018-01-271-0/+130
* clk: aspeed: Register core clocksJoel Stanley2018-01-271-0/+177
* clk: Add clock driver for ASPEED BMC SoCsJoel Stanley2018-01-271-0/+141
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