| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: aspeed: Handle inverse polarity of USB port 1 clock gate | Benjamin Herrenschmidt | 2018-01-27 | 1 | -3/+12 |
| * | clk: aspeed: Fix return value check in aspeed_cc_init() | Wei Yongjun | 2018-01-27 | 1 | -1/+1 |
| * | clk: aspeed: Add reset controller | Joel Stanley | 2018-01-27 | 1 | -1/+81 |
| * | clk: aspeed: Register gated clocks | Joel Stanley | 2018-01-27 | 1 | -0/+130 |
| * | clk: aspeed: Add platform driver and register PLLs | Joel Stanley | 2018-01-27 | 1 | -0/+130 |
| * | clk: aspeed: Register core clocks | Joel Stanley | 2018-01-27 | 1 | -0/+177 |
| * | clk: Add clock driver for ASPEED BMC SoCs | Joel Stanley | 2018-01-27 | 1 | -0/+141 |
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