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path: root/drivers/clk/clk-versaclock3.c (follow)
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* clk: versaclock3: Drop ret variableBiju Das2023-12-181-19/+11
| | | | | | | | | | | Drop ret variable from vc3_clk_mux_determine_rate(). While at it, return the value returned by regmap_* wherever possible instead of returning 0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-6-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: versaclock3: Add missing space between ')' and '{'Biju Das2023-12-181-22/+22
| | | | | | | | | | | Add missing space between ')' and '{' for hw.init initialization. While at it, update the macro VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a->0xa. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-5-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: versaclock3: Use u8 return type for get_parent() callbackBiju Das2023-12-181-3/+3
| | | | | | | | | The return type of get_parent() member in struct clk_ops is u8. Use same return type for corresponding callback function as well. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-4-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: versaclock3: Avoid unnecessary paddingBiju Das2023-12-181-3/+3
| | | | | | | | | Move long/pointer variables at the beginning of struct to avoid unnecessary padding. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-3-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: versaclock3: Update vc3_get_div() to avoid divide by zeroBiju Das2023-12-181-1/+1
| | | | | | | | | | Update vc3_get_div() to avoid divide by zero operation on vc3_div_round_rate() by returning1, if there is no table match found. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20231122142310.203169-2-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
*-. Merge branches 'clk-renesas', 'clk-kunit', 'clk-regmap' and ↵Stephen Boyd2023-10-301-7/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-frac-divider' into clk-next - Make clk kunit tests work with lockdep - Fix clk gate kunit test for big-endian - Convert more than a handful of clk drivers to use regmap maple tree - Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk implementation * clk-renesas: (23 commits) clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R() clk: renesas: Add minimal boot support for RZ/G3S SoC clk: renesas: rzg2l: Add divider clock for RZ/G3S clk: renesas: rzg2l: Refactor SD mux driver clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header clk: renesas: rzg2l: Add struct clk_hw_data clk: renesas: rzg2l: Add support for RZ/G3S PLL clk: renesas: rzg2l: Remove critical area clk: renesas: rzg2l: Fix computation formula clk: renesas: rzg2l: Trust value returned by hardware clk: renesas: rzg2l: Lock around writes to mux register clk: renesas: rzg2l: Wait for status bit of SD mux before continuing clk: renesas: rcar-gen3: Extend SDnH divider table dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC clk: renesas: r8a7795: Constify r8a7795_*_clks clk: renesas: r9a06g032: Name anonymous structs clk: renesas: r9a06g032: Fix kerneldoc warning clk: renesas: rzg2l: Use u32 for flag and mux_flags clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields ... * clk-kunit: clk: Fix clk gate kunit test on big-endian CPUs clk: Parameterize clk_leaf_mux_set_rate_parent clk: Drive clk_leaf_mux_set_rate_parent test from clk_ops * clk-regmap: clk: versaclock7: Convert to use maple tree register cache clk: versaclock5: Convert to use maple tree register cache clk: versaclock3: Convert to use maple tree register cache clk: versaclock3: Remove redundant _is_writeable() clk: si570: Convert to use maple tree register cache clk: si544: Convert to use maple tree register cache clk: si5351: Convert to use maple tree register cache clk: si5341: Convert to use maple tree register cache clk: si514: Convert to use maple tree register cache clk: cdce925: Convert to use maple tree register cache * clk-frac-divider: clk: fractional-divider: tests: Add test suite for edge cases clk: fractional-divider: Improve approximation when zero based and export
| | * clk: versaclock3: Convert to use maple tree register cacheMark Brown2023-10-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230929-clk-maple-versaclk-v1-2-24dd5b3d8689@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| | * clk: versaclock3: Remove redundant _is_writeable()Mark Brown2023-10-101-6/+0
| |/ | | | | | | | | | | | | | | | | | | | | The versaclock3 driver provides an _is_writeable() function which returns true for all registers. This is the default assumption for regmaps so we can remove the function for a very minor improvement in performance and code size. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20230929-clk-maple-versaclk-v1-1-24dd5b3d8689@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: vc3: Make vc3_clk_mux enum values based on vc3_clk enum valuesBiju Das2023-09-111-8/+8
| | | | | | | | | | | | | | | | | | | | Make vc3_clk_mux enum values depend upon vc3_clk enum values to avoid any accidental breakage in the future. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20230824104812.147775-5-biju.das.jz@bp.renesas.com Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: vc3: Fix output clock mappingBiju Das2023-09-111-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Table 3. ("Output Source") in the 5P35023 datasheet, the output clock mapping should be 0=REF, 1=SE1, 2=SE2, 3=SE3, 4=DIFF1, 5=DIFF2. But the code uses inverse. Fix this mapping issue. Suggested-by: Geert Uytterhoeven <geert+renesas@glider.be> Closes: https://lore.kernel.org/all/CAMuHMdUHD+bEco=WYTYWsTAyRt3dTQQt4Xpaejss0Y2ZpLCMNg@mail.gmail.com/ Fixes: 6e9aff555db7 ("clk: Add support for versa3 clock driver") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230824104812.147775-4-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: vc3: Fix 64 by 64 divisionBiju Das2023-09-111-3/+2
|/ | | | | | | | | | | | | | | | Fix the below cocci warnings by replacing do_div()->div64_ul() and bound the result with a max value of U16_MAX. cocci warnings: drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. Reported-by: Julia Lawall <julia.lawall@inria.fr> Closes: https://lore.kernel.org/r/202307270841.yr5HxYIl-lkp@intel.com/ Fixes: 6e9aff555db7 ("clk: Add support for versa3 clock driver") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20230824104812.147775-3-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: versaclock3: Switch to use i2c_driver's probe callbackUwe Kleine-König2023-08-011-1/+1
| | | | | | | | | | | | The previous mass switch of clk drivers done in commit 62279db5a323 ("clk: Switch i2c drivers back to use .probe()") was based on v6.4-rc1 Since then this driver was added which needs to be converted back in the same way before eventually .probe_new() can be dropped from struct i2c_driver. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230721071846.111663-1-u.kleine-koenig@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: Add support for versa3 clock driverBiju Das2023-07-201-0/+1143
Add support for Renesas versa3 clock driver(5p35023). The clock generator provides 6 output clocks. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20230705171000.85786-3-biju.das.jz@bp.renesas.com [sboyd@kernel.org: Add newline to printk] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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