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path: root/drivers/clk/clk-versaclock5.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: vc5: Add support for 5P49V60Lars-Peter Clausen2023-01-181-3/+22
* clk: vc5: Use `clamp()` to restrict PLL rangeLars-Peter Clausen2023-01-181-4/+1
* clk: Remove a useless includeChristophe JAILLET2022-11-231-1/+0
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2022-10-081-58/+105
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| *---. Merge branches 'clk-baikal', 'clk-broadcom', 'clk-vc5' and 'clk-versaclock' i...Stephen Boyd2022-10-041-57/+104
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| | | | * clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975Matthias Fend2022-10-031-0/+11
| | | | * clk: vc5: Use regmap_{set,clear}_bits() where appropriateLars-Peter Clausen2022-10-011-20/+15
| | | | * clk: vc5: Check IO access resultsLars-Peter Clausen2022-10-011-50/+91
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| | * / clk: vc5: Fix 5P49V6901 outputs disabling when enabling FODSerge Semin2022-09-301-1/+1
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| * / dt-bindings: clock: Move versaclock.h to dt-bindings/clockLukas Bulwahn2022-08-231-1/+1
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* / i2c: Make remove callback return voidUwe Kleine-König2022-08-161-3/+1
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* clk: vc5: Use i2c .probe_newLuca Ceresoli2021-11-021-2/+2
* clk: vc5: Add properties for configuring SD/OE behaviorSean Anderson2021-08-291-0/+24
* clk: vc5: Use dev_err_probeSean Anderson2021-08-291-10/+10
* clk: vc5: fix output disabling when enabling a FODLuca Ceresoli2021-06-091-3/+24
* clk: vc5: Add support for optional load capacitanceAdam Ford2021-02-111-0/+64
* clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"Geert Uytterhoeven2020-12-201-2/+2
* clk: vc5: use a dedicated struct to describe the output driversLuca Ceresoli2020-07-241-9/+15
* clk: vc5: Add memory check to prevent oopsAdam Ford2020-07-231-3/+5
* clk: vc5: fix use of memory after it has been kfree'dColin Ian King2020-07-231-32/+18
* clk: vc5: Enable addition output configurations of the VersaclockAdam Ford2020-06-231-0/+156
* clk: vc5: Allow Versaclock driver to support multiple instancesAdam Ford2020-06-231-47/+37
* clk: vc5: Add support for IDT VersaClock 5P49V6965Adam Ford2020-05-301-0/+11
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner2019-05-301-10/+1
* clk: vc5: Abort clock configuration without upstream clockMarek Vasut2019-01-091-1/+3
* clk: vc5: Add suspend/resume supportMarek Vasut2018-12-141-0/+25
* clk: vc5: Add support for IDT VersaClock 5P49V5925Vladimir Barinov2017-07-171-0/+11
* clk: vc5: Add support for IDT VersaClock 5P49V6901Marek Vasut2017-07-171-0/+11
* clk: vc5: Add support for the input frequency doublerMarek Vasut2017-07-171-1/+77
* clk: vc5: Split clock input mux and predividerMarek Vasut2017-07-171-12/+34
* clk: vc5: Configure the output buffer input mux on prepareMarek Vasut2017-07-171-0/+19
* clk: vc5: Do not warn about disabled output buffer input muxesMarek Vasut2017-07-171-0/+3
* clk: vc5: Fix trivial typoMarek Vasut2017-07-171-1/+1
* clk: vc5: Prevent division by zero on unconfigured outputsMarek Vasut2017-07-171-0/+4
* clk: vc5: Add support for IDT VersaClock 5P49V5935Alexey Firago2017-04-191-2/+13
* clk: vc5: Add structure to describe particular chip featuresAlexey Firago2017-04-191-18/+47
* clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933Marek Vasut2017-01-211-0/+791
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-13 22:01:25 +0100