linux - linux

	Commit message (Expand)	Author	Files	Lines
2020-12-20	dt-bindings: Add Canaan vendor prefix	Damien Le Moal	1	-0/+2
2020-12-20	clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts"	Geert Uytterhoeven	1	-2/+2
2020-12-20	clk: ingenic: Fix divider calculation with div tables	Paul Cercueil	1	-4/+10
2020-12-20	clk: sunxi-ng: Make sure divider tables have sentinel	Jernej Skrabec	2	-0/+2
2020-12-20	clk: s2mps11: Fix a resource leak in error handling paths in the probe function	Christophe JAILLET	1	-0/+1
2020-12-20	clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9	Terry Zhou	1	-2/+2
2020-12-20	clk: si5351: Wait for bit clear after PLL reset	Sascha Hauer	1	-3/+10
2020-12-20	clk: at91: sam9x60: remove atmel,osc-bypass support	Alexandre Belloni	1	-5/+1
2020-12-19	clk: at91: sama7g5: register cpu clock	Claudiu Beznea	2	-7/+7
2020-12-19	clk: at91: clk-master: re-factor master clock	Claudiu Beznea	14	-146/+542
2020-12-19	clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz	Claudiu Beznea	1	-14/+47
2020-12-19	clk: at91: sama7g5: decrease lower limit for MCK0 rate	Claudiu Beznea	1	-1/+1
2020-12-19	clk: at91: sama7g5: remove mck0 from parent list of other clocks	Claudiu Beznea	1	-29/+26
2020-12-19	clk: at91: clk-sam9x60-pll: allow runtime changes for pll	Claudiu Beznea	4	-41/+197
2020-12-19	clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics	Eugen Hristev	1	-2/+2
2020-12-19	clk: at91: clk-master: add 5th divisor for mck master	Eugen Hristev	2	-2/+2
2020-12-19	clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT	Eugen Hristev	1	-2/+4
2020-12-19	dt-bindings: clock: at91: add sama7g5 pll defines	Eugen Hristev	2	-3/+13
2020-12-19	clk: at91: sama7g5: fix compilation error	Claudiu Beznea	1	-2/+4
2020-12-19	clk: bcm: dvp: Add MODULE_DEVICE_TABLE()	Nicolas Saenz Julienne	1	-0/+1
2020-12-19	clk: bcm: dvp: drop a variable that is assigned to only	Uwe Kleine-König	1	-2/+1
2020-12-17	clk: Trace clk_set_rate() "range" functions	Maxime Ripard	2	-0/+50
2020-12-17	clk: axi-clkgen: move the OF table at the bottom of the file	Alexandru Ardelean	1	-9/+9
2020-12-17	clk: axi-clkgen: wrap limits in a struct and keep copy on the state object	Alexandru Ardelean	1	-17/+31
2020-12-17	dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format	Alexandru Ardelean	2	-25/+53
2020-12-17	clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs	David Shah	1	-1/+11
2020-12-17	clk: ti: Fix memleak in ti_fapll_synth_setup	Zhang Qilong	1	-2/+9
2020-12-17	clk: Add hardware-enable column to clk summary	Dmitry Osipenko	1	-4/+11
2020-12-17	clk: mediatek: Make mtk_clk_register_mux() a static function	Weiyi Lu	2	-5/+1
2020-12-16	clk: sifive: Add clock enable and disable ops	Pragnesh Patel	4	-9/+93
2020-12-16	clk: sifive: Fix the wrong bit field shift	Zong Li	1	-2/+2
2020-12-16	clk: sifive: Add a driver for the SiFive FU740 PRCI IP block	Zong Li	7	-3/+369
2020-12-16	clk: sifive: Use common name for prci configuration	Zong Li	3	-5/+5
2020-12-16	clk: sifive: Extract prci core to common base	Zong Li	5	-571/+641