Commit message (Expand) | Author | Files | Lines | |
---|---|---|---|---|
2018-09-11 | clk: renesas: r8a77970: Add TMU clocks | Sergei Shtylyov | 1 | -0/+5 |
2018-09-11 | clk: renesas: r8a77970: Add CMT clocks | Sergei Shtylyov | 1 | -0/+4 |
2018-09-11 | clk: renesas: r9a06g032: Fix UART34567 clock rate | Phil Edworthy | 1 | -1/+2 |
2018-09-03 | clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI | Sergei Shtylyov | 2 | -2/+67 |
2018-09-03 | clk: renesas: r8a77980: Add CMT clocks | Sergei Shtylyov | 1 | -0/+4 |
2018-08-31 | clk: renesas: r8a77990: Add missing I2C7 clock | Geert Uytterhoeven | 1 | -0/+1 |
2018-08-28 | clk: renesas: r8a77965: Add FDP clock | Hoan Nguyen An | 1 | -0/+1 |
2018-08-27 | clk: renesas: cpg-mssr: Add r8a774a1 support | Biju Das | 6 | -4/+341 |