| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: hi3620: add gate clock flag | Haojian Zhuang | 2013-12-11 | 1 | -59/+59 |
| * | clk: hi3620: fix wrong flags on divider | Haojian Zhuang | 2013-12-11 | 1 | -11/+11 |
| * | clk: hisilicon: add common clock support | Haojian Zhuang | 2013-12-04 | 5 | -0/+651 |
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