summaryrefslogtreecommitdiffstats
path: root/drivers/clk/imx/clk-imx8mm.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slicePeng Fan2020-05-211-9/+9
* clk: imx8m: migrate A53 clk root to use composite corePeng Fan2020-05-201-3/+3
* clk: imx8m: drop clk_hw_set_parent for A53Peng Fan2020-05-201-3/+0
* clk: imx8mm: A53 core clock no need to be criticalAnson Huang2020-03-111-4/+4
* clk: imx: imx8mm: fix a53 cpu clockPeng Fan2020-02-241-4/+12
* clk: imx8mm: Remove unused includesAnson Huang2020-02-191-2/+0
* clk: imx8mm: Add missing of_node_put()Anson Huang2020-02-171-0/+1
* clk: imx: Include clk-provider.h instead of clk.h for i.MX8M SoCs clock driverAnson Huang2020-02-171-1/+1
* clk: imx8mm: Add CLKO2 supportFabio Estevam2020-02-171-0/+3
* clk: imx8mm: Fix the CLKO1 source select listFabio Estevam2020-02-171-2/+2
* clk: imx: imx8mm: use imx8m_clk_hw_composite_corePeng Fan2020-02-141-14/+21
* clk: imx: imx8mm: Switch to clk_hw based APIPeng Fan2019-12-231-271/+284
* clk: imx8m: Suppress bind attrsLeonard Crestez2019-12-091-0/+5
* clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHELeonard Crestez2019-12-091-1/+1
* clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocksLeonard Crestez2019-12-091-2/+7
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-12-021-102/+48
|\
| * clk: imx: imx8mm: mark sys_pll1/2 as fixed clockPeng Fan2019-10-251-26/+20
| * clk: imx8mm: Define gates for pll1/2 fixed dividersLeonard Crestez2019-10-251-19/+38
| * clk: imx8mm: Move 1443X/1416X PLL clock structure to common placeAnson Huang2019-10-061-77/+10
* | clk: imx8m: Use SYS_PLL1_800M as intermediate parent of CLK_ARMLeonard Crestez2019-10-281-1/+1
|/
* clk: imx: imx8mm: fix pll mux bitPeng Fan2019-09-181-22/+10
* clk: imx8mm: Fix incorrect parentsLeonard Crestez2019-08-191-4/+4
* clk: imx8mm: Unregister clks when of_clk_add_provider failedAnson Huang2019-08-121-1/+6
* clk: imx8mm: Switch to platform driverAbel Vesa2019-08-031-21/+36
* clk: imx: imx8mm: fix audio pll settingPeng Fan2019-08-031-2/+2
* clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80mAnson Huang2019-08-031-1/+1
* clk: imx8mm: Fix typo of pwm3 clock's mux option #4Anson Huang2019-08-031-1/+1
* clk: imx8mm: rename 'share_count_dcss' to 'share_count_disp'Fancy Fang2019-08-031-5/+5
* clk: imx8mm: correct the usb1_ctrl parent to be usb_busLi Jun2019-08-031-1/+1
* clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usageAnson Huang2019-08-031-17/+0
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-171-4/+14
|\
| * clk: imx: imx8mm: correct audio_pll2_clk to audio_pll2_outPeng Fan2019-06-071-3/+3
| * clk: imx8mm: Mark dram_apb criticalLeonard Crestez2019-05-231-1/+1
| * clk: imx8m: Add GIC clockLeonard Crestez2019-05-231-0/+4
| * clk: imx8mm: add SNVS clock to clock treeAnson Huang2019-05-231-0/+1
| * clk: imx8mm: add GPIO clocks to clock treeAnson Huang2019-05-201-0/+5
* | clk: imx: imx8mm: fix int pll clk gatePeng Fan2019-05-211-6/+6
|/
* clk: imx: imx8mm: Mark init function __initStephen Boyd2019-02-221-1/+1
* clk: imx: Add clock driver support for imx8mmBai Ping2019-02-211-0/+675
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 02:58:20 +0100