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* clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular compositesAlexander Stein2021-11-051-2/+2
| | | | | | | | | | | Only imx8m_clk_hw_composite_core needs to set this flag. Fixes: a60fe746df94 ("clk: imx: Rework all imx_clk_hw_composite wrappers") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20211103123947.3222443-1-alexander.stein@ew.tq-group.com Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: Make CLK_IMX8ULP select MXC_CLKFabio Estevam2021-10-061-0/+1
| | | | | | | | | | | | | | | | | | | | Building CLK_IMX8ULP without selecting MXC_CLK causes the following build errors: ld: drivers/clk/imx/clk-imx8ulp.o: in function `imx8ulp_clk_cgc2_init': clk-imx8ulp.c:(.text+0xd0): undefined reference to `imx_ccm_lock' ld: clk-imx8ulp.c:(.text+0x14f): undefined reference to `imx_clk_hw_pllv4' ld: clk-imx8ulp.c:(.text+0x15a): undefined reference to `imx_ccm_lock' Avoid this problem by making CLK_IMX8ULP select MXC_CLK. Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp") Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20211006190008.1935051-1-festevam@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: imx6ul: Fix csi clk gate registerStefan Riedmueller2021-10-011-1/+6
| | | | | | | | | | | | | | | | | According to the imx6ul Reference Manual the csi clk gate register is CCM_CCGR3 (offset 0x74) bit 0/1. For the imx6ull on the other hand the Reference Manual lists register CCM_CCGR2 (offset 0x70) bit 2/3 as the csi clk gate which is the current setting. Tests have shown though that the correct csi clk gate register for the imx6ull is actually CCM_CCGR3 bit 0/1 as well. Thus set the correct register for both platforms. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Tested-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210927072857.3940880-2-s.riedmueller@phytec.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: imx6ul: Move csi_sel mux to correct base registerStefan Riedmueller2021-10-011-1/+1
| | | | | | | | | | | | | | | | | The csi_sel mux register is located in the CCM register base and not the CCM_ANALOG register base. So move it to the correct position in code. Otherwise changing the parent of the csi clock can lead to a complete system failure due to the CCM_ANALOG_PLL_SYS_TOG register being falsely modified. Also remove the SET_RATE_PARENT flag since one possible supply for the csi_sel mux is the system PLL which we don't want to modify. Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210927072857.3940880-1-s.riedmueller@phytec.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: Fix the build break when clk-imx8ulp build as moduleJacky Bai2021-10-013-0/+3
| | | | | | | | | | | Export the necessary symbols to fix the build break when clk-imx8ulp build as module Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp") Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210917061629.3798360-1-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: Add the pcc reset controller support on imx8ulpJacky Bai2021-09-302-3/+123
| | | | | | | | | | | | | | | | | On i.MX8ULP, for some of the PCCs, it has a peripheral SW RST bit resides in the same registers as the clock controller. So add this SW RST controller support alongs with the pcc clock initialization. the reset and clock shared the same register, to avoid accessing the same register by reset control and clock control concurrently, locking is necessary, so reuse the imx_ccm_lock spinlock to simplify the code. Suggested-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-10-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: Add clock driver for imx8ulpJacky Bai2021-09-303-0/+467
| | | | | | | | | | Add clock driver for i.MX8ULP. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-9-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: Update the pfdv2 for 8ulp specific supportJacky Bai2021-09-303-13/+21
| | | | | | | | | | | | On i.MX8ULP, the 'CLK_SET_RATE_PARENT' flag should NOT be set and according to the laest RM, the PFD divider value range seems will be changed in the future, so update the pfdv2 to include the specific support for i.MX8ULP. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-8-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: disable the pfd when set pfdv2 clock rateJacky Bai2021-09-301-2/+11
| | | | | | | | | | | | | | It is possible that a PFD is enabled in HW but not in SW. That means the enable count & prepare count of the PFD clock is '0', so the 'CLK_SET_RATE' flag can do nothing when the rate is changed while the PFD is hw enabled. In order to safely change the pfd rate, we can disable the PFD directly if it is hw enabled but not used by SW end user. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-7-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: Add 'CLK_SET_RATE_NO_REPARENT' for composite-7ulpJacky Bai2021-09-301-1/+1
| | | | | | | | | | | | | | | | For the imx_composite-7ulp clock type, The clock parent should be changed explicitly by end user of this clock, if the the 'CLK_SET_RATE_NO_REPARENT' flag is not set, when user want to set a clock frequency that can NOT get from HW accurately, then the clock's parent will be switch to another clock parent sometimes. This is NOT what we expected and introduced some additional debug effort, so add the 'CLK_SET_RATE_NO_REPARENT' to avoid such unexpected result. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-6-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: disable i.mx7ulp composite clock during initializationAnson Huang2021-09-301-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX7ULP peripheral clock ONLY allow parent/rate to be changed with clock gated, however, during clock tree initialization, the peripheral clock could be enabled by bootloader, but the prepare count in clock tree is still zero, so clock core driver will allow parent/rate changed even with CLK_SET_RATE_GATE/CLK_SET_PARENT_GATE set, but the change will fail due to HW NOT allow parent/rate change with clock enabled. It will cause clock HW status mismatch with clock tree info and lead to function issue. Below is an example: usdhc0's pcc clock value is 0xC5000000 during kernel boot up, it means usdhc0 clock is enabled, its parent is APLL_PFD1. In DT file, the usdhc0 clock settings are as below: assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>; when kernel boot up, the clock tree info is as below, but the usdhc0 PCC register is still 0xC5000000, which means its parent is still from APLL_PFD1, which is incorrect and cause usdhc0 NOT work. nic1_clk 2 2 0 176000000 0 0 50000 usdhc0 0 0 0 176000000 0 0 50000 After making sure the peripheral clock is disabled during clock tree initialization, the usdhc0 is working, and this change is necessary for all i.MX7ULP peripheral clocks. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-5-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: Update the compsite driver to support imx8ulpJacky Bai2021-09-302-3/+64
| | | | | | | | | | | | | On i.MX8ULP, some peripherals have a sw_rst control resides in the per device PCC clock control register, all others are same as i.MX7ULP, so update the 7ulp clock composite driver to support i.MX8ULP to maxmimize the code reuse. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-4-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: Update the pllv4 to support imx8ulpJacky Bai2021-09-303-13/+34
| | | | | | | | | | | The PLLs used on i.MX8ULP is mostly the same as on i.MX7ULP, except the PLL register offset is changed. Change the PLLv4 driver for code reuse on i.MX7ULP and i.MX8ULP. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210914065208.3582128-3-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: Rework imx_clk_hw_pll14xx wrapperAbel Vesa2021-09-301-7/+3
| | | | | | | | | | It looks much cleaner to just have a macro compared to having a function that passes NULL as dev to the lower-level imx_dev_clk_hw_pll14xx. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-9-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: Rework all imx_clk_hw_composite wrappersAbel Vesa2021-09-302-32/+36
| | | | | | | | | | | | | | Rather than having multiple different macros for each different type of imx8m_clk_hw_composite, implement them in such a way so we can take advantage the most of the already defined simpler types. Basically, we end up having one low-level __imx8m_clk_hw_composite function, a wrapper to simplify the parents related arguments called _imx8m_clk_hw_composite and then all the types can use those for each specific case. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-8-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: Rework all clk_hw_register_divider wrappersAbel Vesa2021-09-301-18/+11
| | | | | | | | | | | Instead of having multiple inline functions that were calling clk_hw_register_divider, implement a generic low-level __imx_clk_hw_divider and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-7-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: Rework all clk_hw_register_mux wrappersAbel Vesa2021-09-301-46/+22
| | | | | | | | | | | Instead of having multiple inline functions that were calling clk_hw_register_mux, implement a generic low-level __imx_clk_hw_mux and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-6-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: Rework all clk_hw_register_gate2 wrappersAbel Vesa2021-09-301-51/+26
| | | | | | | | | | | Instead of having multiple inline functions that were calling clk_hw_register_gate2, implement a generic low-level __imx_clk_hw_gate2 and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-5-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: Rework all clk_hw_register_gate wrappersAbel Vesa2021-09-171-41/+23
| | | | | | | | | | | Instead of having multiple inline functions that were calling clk_hw_register_gate, implement a generic low-level __imx_clk_hw_gate and implement the rest as macros that pass on as arguments whatever is needed in each case. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-4-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: Make mux/mux2 clk based helpers use clk_hw based onesAbel Vesa2021-09-171-20/+6
| | | | | | | | | | Implement the clk based helpers as macros rather than as inline functions. Once all the provider drivers have switch to clk_hw, all the clk based macros will go away. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-3-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: Remove unused helpersAbel Vesa2021-09-171-103/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove all the helpers that are not referenced anywhere anymore. Most of them are not clk_hw based. The rest are passing the device as an argument and were intented for BLK_CTL driver usage, but that is not the case anymore since the BLK_CTL is (or will be) implemented outside of CCF. - imx_clk_divider2 - imx_clk_gate2_shared2 - imx_clk_gate3 - imx_clk_gate4 - imx_clk_frac_pll - imx_clk_sscg_pll - imx_clk_pll14xx - imx_clk_pll14xx - imx_clk_divider2_flags - imx_dev_clk_hw_gate - imx_dev_clk_hw_gate_shared - imx_clk_gate3_flags - imx_clk_gate4_flags - imx_dev_clk_hw_mux - imx_clk_mux2 - imx_dev_clk_hw_mux_flags - imx8m_clk_composite_flags - __imx8m_clk_composite - imx8m_clk_composite - imx8m_clk_composite_critical Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/1631521490-17171-2-git-send-email-abel.vesa@nxp.com Reviewed-by: Stephen Boyd <sboyd@kernel.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2021-09-027-21/+43
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Nothing changed in the clk framework core this time around. We did get some updates to the basic clk types to use determine_rate for the divider type and add a power of two fractional divider flag though. Otherwise, this is a collection of clk driver updates. More than half the diffstat is in the Qualcomm clk driver where we add a bunch of data to describe clks on various SoCs and fix bugs. The other big new thing in here is the Mediatek MT8192 clk driver. That's been under review for a while and it's nice to see that it's finally upstream. Beyond that it's the usual set of minor fixes and tweaks to clk drivers. There are some non-clk driver bits in here which have all been acked by the respective maintainers. New Drivers: - Support video, gpu, display clks on qcom sc7280 SoCs - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs - Multimedia clks (MMCC) on qcom MSM8994/MSM8992 - RPMh clks on qcom SM6350 SoCs - Support for Mediatek MT8192 SoCs - Add display (DU and DSI) clocks on Renesas R-Car V3U - Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and resets on Renesas RZ/G2L Updates: - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators - Add power of two flag to fractional divider clk type - Migrate some clk drivers to clk_divider_ops.determine_rate - Migrate to clk_parent_data in gcc-sdm660 - Fix CLKOUT clocks on i.MX8MM and i.MX8MN by using imx_clk_hw_mux2 - Switch from .round_rate to .determine_rate in clk-divider-gate - Fix clock tree update for TF-A controlled clocks for all i.MX8M - Add missing M7 core clock for i.MX8MN - YAML conversion of rk3399 clock controller binding - Removal of GRF dependency for the rk3328/rk3036 pll types - Drop CLK_IS_CRITICAL flag from Tegra fuse clk - Make CLK_R9A06G032 Kconfig symbol invisible - Convert various DT bindings to YAML" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (128 commits) dt-bindings: clock: samsung: fix header path in example clk: tegra: fix old-style declaration clk: qcom: Add SM6350 GCC driver MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema dt-bindings: clock: samsung: convert Exynos AudSS to dtschema dt-bindings: clock: samsung: convert Exynos4 to dtschema dt-bindings: clock: samsung: convert Exynos3250 to dtschema dt-bindings: clock: samsung: convert Exynos542x to dtschema dt-bindings: clock: samsung: add bindings for Exynos external clock dt-bindings: clock: samsung: convert Exynos5250 to dtschema clk: vc5: Add properties for configuring SD/OE behavior clk: vc5: Use dev_err_probe dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin dt-bindings: clock: brcm,iproc-clocks: fix armpll properties clk: zynqmp: Fix kernel-doc format clk: at91: clk-generated: Limit the requested rate to our range clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates clk: zynqmp: Fix a memory leak clk: zynqmp: Check the return type ...
| *-. Merge branches 'clk-kirkwood', 'clk-imx', 'clk-doc', 'clk-zynq' and ↵Stephen Boyd2021-09-026-21/+42
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-ralink' into clk-next * clk-kirkwood: clk: kirkwood: Fix a clocking boot regression * clk-imx: clk: imx8mn: Add M7 core clock clk: imx8m: fix clock tree update of TF-A managed clocks clk: imx: clk-divider-gate: Switch to clk_divider.determine_rate clk: imx8mn: use correct mux type for clkout path clk: imx8mm: use correct mux type for clkout path * clk-doc: dt-bindings: clock: samsung: fix header path in example MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema dt-bindings: clock: samsung: convert Exynos AudSS to dtschema dt-bindings: clock: samsung: convert Exynos4 to dtschema dt-bindings: clock: samsung: convert Exynos3250 to dtschema dt-bindings: clock: samsung: convert Exynos542x to dtschema dt-bindings: clock: samsung: add bindings for Exynos external clock dt-bindings: clock: samsung: convert Exynos5250 to dtschema dt-bindings: clock: brcm,iproc-clocks: fix armpll properties clk: zynqmp: Fix kernel-doc format clk: at91: sama7g5: remove all kernel-doc & kernel-doc warnings clk: zynqmp: fix kernel doc * clk-zynq: clk: zynqmp: Fix a memory leak clk: zynqmp: Check the return type * clk-ralink: clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates
| | | * clk: imx8mn: Add M7 core clockMarek Vasut2021-08-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing M7 core clock entry to the iMX8MN clock driver. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Link: https://lore.kernel.org/r/20210819202036.2084782-1-marex@denx.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
| | | * clk: imx8m: fix clock tree update of TF-A managed clocksAhmad Fatoum2021-08-245-12/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the SiP and then does clk_set_parent on the DDR muxes to synchronize the clock tree. Since 936c383673b9 ("clk: imx: fix composite peripheral flags"), these TF-A managed muxes have SET_PARENT_GATE set, which results in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY: echo 25000000 > userspace/set_freq imx8m-ddrc-devfreq 3d400000.memory-controller: failed to set dram_apb parent: -16 Fix this by adding a new i.MX composite flag for firmware managed clocks, which clears SET_PARENT_GATE. This is safe to do, because updating the Linux clock tree to reflect reality will always be glitch-free. Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210810151432.9228-1-a.fatoum@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
| | | * clk: imx: clk-divider-gate: Switch to clk_divider.determine_rateMartin Blumenstingl2021-08-241-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | .determine_rate is meant to replace .round_rate in CCF in the future. Switch over to .determine_rate now that clk_divider_ops has gained support for that. Cc: Guenter Roeck <linux@roeck-us.net> Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210702225145.2643303-3-martin.blumenstingl@googlemail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
| | | * clk: imx8mn: use correct mux type for clkout pathLucas Stach2021-08-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mux in the clkout path needs the current selected parent to be enabled for the switch to work. Use the correct mux type to have the clk framework take care of this requirement. Fixes: af4df655040 ("clk: imx8mn: add clkout1/2 support") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210628211554.2510238-2-l.stach@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
| | | * clk: imx8mm: use correct mux type for clkout pathLucas Stach2021-08-241-2/+2
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mux in the clkout path needs the current selected parent to be enabled for the switch to work. Use the correct mux type to have the clk framework take care of this requirement. Fixes: c1ae5c6f789a ("clk: imx8mm: add clkout1/2 support") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Link: https://lore.kernel.org/r/20210628211554.2510238-1-l.stach@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
| * / clk: fractional-divider: Hide clk_fractional_divider_ops from wide audienceAndy Shevchenko2021-08-121-0/+1
| |/ | | | | | | | | | | | | | | | | | | The providers are all located in drivers/clk/ and hence no need to export the clock operations to wider audience. Hide them by moving to drivers/clk/clk-fractional-divider.h. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210812170025.67074-2-andriy.shevchenko@linux.intel.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* / clk: imx6q: fix uart earlycon unworkDong Aisheng2021-08-061-1/+1
|/ | | | | | | | | | | | | | | The earlycon depends on the bootloader setup UART clocks being retained. There're actually two uart clocks (ipg, per) on MX6QDL, but the 'Fixes' commit change to register only one which means another clock may be disabled during booting phase and result in the earlycon unwork. Cc: stable@vger.kernel.org # v5.10+ Fixes: 379c9a24cc23 ("clk: imx: Fix reparenting of UARTs not associated with stdout") Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20210702085438.1988087-1-aisheng.dong@nxp.com Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx8mq: remove SYS PLL 1/2 clock gatesLucas Stach2021-06-141-38/+18
| | | | | | | | | | | | | Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks the uSDHC module which is sporadically unable to enumerate devices after this change. Also it makes AMP clock management harder with no obvious benefit to Linux, so just revert the change. Link: https://lore.kernel.org/r/20210528180135.1640876-1-l.stach@pengutronix.de Fixes: b04383b6a558 ("clk: imx8mq: Define gates for pll1/2 fixed dividers") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: Do not enable runtime PM for CPU clksNitin Garg2021-06-141-12/+18
| | | | | | | | | | | Since CPU clocks are managed by CPUFREQ and ATF, do not enable runtime PM otherwise rpm gets out of status as cpufreq also manages clock states. Signed-off-by: Nitin Garg <nitin.garg@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: add parent save and restoreDong Aisheng2021-06-141-1/+28
| | | | | | | | Add clock parent save and restore. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: Only save DC SS clock using non-cached clock rateAnson Huang2021-06-141-1/+8
| | | | | | | | | | | | | Display sub-system has special clock settings in SCFW, the bypassed clock is used instead of PLL in Linux kernel clock tree, so when saving clock rate, need to save non-cached clock rate for Display sub-system's bypass clocks, and other clocks still use the cached clock rate which is with runtime PM ON. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: Add A72 frequency scaling supportAnson Huang2021-06-141-1/+3
| | | | | | | | | Add A72 clock to support cpufreq on A72 cluster. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: Add A53 frequency scaling supportAnson Huang2021-06-141-2/+2
| | | | | | | | | Add i.MX8QM cpufreq support for A53 cluster. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: bypass pi_pll enable status restoreDong Aisheng2021-06-141-1/+1
| | | | | | | | | PI PLL does not support enable/disable. So bypass it's enable status restore. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: detach pd if can't power upDong Aisheng2021-06-141-0/+1
| | | | | | | | | detach pd if can't power up as it may be allocated to a differet partition. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: bypass cpu clock save and restoreDong Aisheng2021-06-141-0/+10
| | | | | | | | CPU clock is managed by ATF. No need save and restore. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: add parallel port clock opsGuoniu.zhou2021-06-141-0/+8
| | | | | | | | | | | Because digital pll for parallel interface is on by default, and not provide enable/disable function by scu, so add the related ops for this kind of clocks. Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: add more scu clocksDong Aisheng2021-06-141-2/+150
| | | | | | | | Add more scu clocks used by i.MX8 platforms. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: add enet rgmii gpr clocksDong Aisheng2021-06-141-4/+18
| | | | | | | | | | | | enet tx clk actually is sourced from a gpr divider, not default enet clk. Add enet grp clocks for user to use correctly. Cc: Abel Vesa <abel.vesa@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx8qm: add clock valid resource checkingDong Aisheng2021-06-144-1/+119
| | | | | | | | Add imx8qm clock valid resource checking mechanism Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx8qxp: add clock valid checking mechnismDong Aisheng2021-06-145-8/+137
| | | | | | | | | | | clk-imx8qxp is a common SCU clock driver used by both QM and QXP platforms. The clock numbers vary a bit between those two platforms. This patch introduces a mechanism to only register the valid clocks for one platform by checking the clk resource id table. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: add gpr clocks supportDong Aisheng2021-06-142-0/+215
| | | | | | | | | | SCU clock protocol supports a few clocks based on GPR controller registers including mux/divider/gate. Add a generic clock register API to support them all. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: scu: remove legacy scu clock binding supportDong Aisheng2021-06-142-135/+81
| | | | | | | | | | | | Legacy scu clock binding are not maintained anymore, it has a very limited clocks supported during initial upstreaming and obviously unusable by products. So it's meaningless to keep it in kernel which worse the code readability. Remove it to keep code much cleaner. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: Remove the audio ipg clock from imx8mpJacky Bai2021-06-141-1/+0
| | | | | | | | | There is no audio ipg clock on i.MX8MP, so remove this from the clock driver. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx: Reference preceded by freeJian Dong2021-04-042-0/+2
| | | | | | | | When register failed, clk will be freed, it will generate dangling pointer problem in later reference. it should return directly. Signed-off-by: Jian Dong <dongjian@yulong.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx8mq: Correct the pcie1 selsRichard Zhu2021-04-041-2/+2
| | | | | | | | | | - The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock. Change the sys2_pll_500m to sys2_pll_50m. - Correct one misspell of the imx8mq_pcie1_ctrl_sels definition, from "sys2_pll_250m" to "sys2_pll_333m". Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
* clk: imx8mp: Remove the none exist pcie clocksRichard Zhu2021-04-041-15/+0
| | | | | | | | | | | | | | In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external OSC or internal system PLL. It is configured in the IOMUX_GPR14 register directly, and can't be contolled by CCM at all. Remove the PCIE PHY clock from clock driver to clean up codes. There is only one PCIe in i.MX8MP, remove the none exist second PCIe related clocks. Remove the none exsits clocks IDs together. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jason Liu <jason.hui.liu@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-15 07:20:29 +0100