linux - linux

	Commit message (Expand)	Author	Age	Files	Lines
*	clk: X1000: Add support for calculat REFCLK of USB PHY.	周琰杰 (Zhou Yanjie)	2020-07-28	1	-1/+83
*	clk: JZ4780: Reformat the code to align it.	周琰杰 (Zhou Yanjie)	2020-07-28	1	-45/+45
*	clk: JZ4780: Add functions for enable and disable USB PHY.	周琰杰 (Zhou Yanjie)	2020-07-28	1	-30/+35
*	clk: Ingenic: Add RTC related clocks for Ingenic SoCs.	周琰杰 (Zhou Yanjie)	2020-07-28	3	-0/+38
*	clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused	Stephen Boyd	2020-05-29	1	-1/+1
*	clk: X1000: Add FIXDIV for SSI clock of X1000.	周琰杰 (Zhou Yanjie)	2020-05-29	1	-6/+111
*	clk: Ingenic: Add CGU driver for X1830.	周琰杰 (Zhou Yanjie)	2020-05-29	3	-0/+459
*	clk: Ingenic: Adjust cgu code to make it compatible with X1830.	周琰杰 (Zhou Yanjie)	2020-05-29	7	-4/+41
*	clk: Ingenic: Remove unnecessary spinlock when reading registers.	周琰杰 (Zhou Yanjie)	2020-05-29	1	-11/+1
*	clk: ingenic/TCU: Fix round_rate returning error	Paul Cercueil	2020-03-21	1	-1/+1
*	clk: ingenic/jz4770: Exit with error if CGU init failed	Paul Cercueil	2020-03-21	1	-1/+3
*	clk: JZ4780: Add function for enable the second core.	周琰杰 (Zhou Yanjie)	2020-03-21	1	-5/+50
*	clk: Ingenic: Add support for TCU of X1000.	周琰杰 (Zhou Yanjie)	2020-03-21	1	-0/+8
*-.	Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ...	Stephen Boyd	2019-11-27	3	-1/+286
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\| * \|	clk: ingenic: Allow drivers to be built with COMPILE_TEST	Stephen Boyd	2019-11-22	1	-1/+1
\| * \|	clk: Ingenic: Add CGU driver for X1000.	Zhou Yanjie	2019-11-14	3	-0/+285
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* /	drivers/clk: convert VL struct to struct_size	Stephen Kitt	2019-11-08	1	-2/+1
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*	Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux	Linus Torvalds	2019-09-22	4	-1/+490
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\| *	clk: jz4740: Add TCU clock	Paul Cercueil	2019-08-09	1	-0/+6
\| *	clk: ingenic: Add driver for the TCU clocks	Paul Cercueil	2019-08-09	3	-1/+484
* \|	clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro	Paul Cercueil	2019-08-12	4	-4/+4
* \|	clk: ingenic/jz4740: Fix "pll half" divider not read/written properly	Paul Cercueil	2019-08-07	1	-1/+8
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*	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	2019-07-17	9	-128/+192
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\| *	clk: ingenic: Remove unused functions	Paul Cercueil	2019-06-26	1	-73/+0
\| *	clk: ingenic: Handle setting the Low-Power Mode bit	Paul Cercueil	2019-06-26	7	-32/+69
\| *	clk: ingenic: Add missing header in cgu.h	Paul Cercueil	2019-06-26	1	-0/+1
\| *	clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly	Paul Cercueil	2019-06-07	1	-1/+8
\| *	clk: ingenic/jz4725b: Fix incorrect dividers for main clocks	Paul Cercueil	2019-06-07	1	-5/+24
\| *	clk: ingenic/jz4770: Fix incorrect dividers for main clocks	Paul Cercueil	2019-06-07	1	-6/+28
\| *	clk: ingenic/jz4740: Fix incorrect dividers for main clocks	Paul Cercueil	2019-06-07	1	-5/+24
\| *	clk: ingenic: Add support for divider tables	Paul Cercueil	2019-06-07	2	-6/+38
* \|	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	Thomas Gleixner	2019-05-30	4	-40/+4
* \|	treewide: Add SPDX license identifier - Makefile/Kconfig	Thomas Gleixner	2019-05-21	2	-0/+2
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*	clk: Remove io.h from clk-provider.h	Stephen Boyd	2019-05-15	4	-0/+4
*	clk: ingenic: jz4725b: Add UDC PHY clock	Paul Cercueil	2019-04-11	1	-0/+6
*	clk: ingenic: Remove set but not used variable 'enable'	YueHaibing	2019-02-26	1	-2/+1
*	clk: ingenic: Fix doc of ingenic_cgu_div_info	Paul Cercueil	2019-02-22	1	-1/+1
*	clk: ingenic: Fix round_rate misbehaving with non-integer dividers	Paul Cercueil	2019-02-22	1	-5/+5
*	clk: ingenic: jz4740: Fix gating of UDC clock	Paul Cercueil	2019-02-05	1	-1/+1
*	clk: Add Ingenic jz4725b CGU driver	Paul Cercueil	2018-10-17	3	-0/+236
*	clk: ingenic: Add proper Kconfig entries	Paul Cercueil	2018-10-17	2	-4/+41
*	clk: ingenic: Add missing flag for UDC clock	Paul Cercueil	2018-07-06	1	-1/+1
*	clk: ingenic: Fix incorrect data for the i2s clock	Paul Cercueil	2018-07-06	1	-1/+1
*	docs: Fix some broken references	Mauro Carvalho Chehab	2018-06-15	1	-1/+1
*	clk: ingenic: jz4770: Add 150us delay after enabling VPU clock	Paul Cercueil	2018-06-02	1	-1/+1
*	clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock	Paul Cercueil	2018-06-02	1	-2/+2
*	clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle	Paul Cercueil	2018-06-02	1	-1/+2
*	clk: ingenic: jz4770: Change OTG from custom to standard gated clock	Paul Cercueil	2018-06-02	1	-37/+5
*	clk: ingenic: Support specifying "wait for clock stable" delay	Paul Cercueil	2018-06-02	2	-0/+5
*	clk: ingenic: Add support for clocks whose gate bit is inverted	Paul Cercueil	2018-06-02	2	-2/+5