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path: root/drivers/clk/mediatek/clk-pll.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: mediatek: Allow changing PLL rate when it is offJames Liao2019-04-111-11/+2
* clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_dataWeiyi Lu2019-04-111-6/+11
* clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_dataOwen Chen2019-04-111-4/+11
* clk: mediatek: Disable tuner_en before change PLL rateOwen Chen2019-04-111-14/+34
* clk: mediatek: add the option for determining PLL source clockChen Zhong2017-11-021-1/+4
* clk: mediatek: Add MT2712 clock supportweiyi.lu@mediatek.com2017-11-021-2/+11
* clk: mediatek: Add MT2701 clock supportShunli Wang2016-11-091-0/+1
* clk: mediatek: remove __init from clk registration functionsJames Liao2016-08-191-1/+1
* clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao2015-10-011-6/+1
* clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao2015-07-281-3/+15
* clk: mediatek: Fix calculation of PLL rate settingsJames Liao2015-07-281-2/+2
* clk: mediatek: Fix PLL registers setting flowJames Liao2015-07-281-9/+12
* clk: mediatek: Initialize clk_init_dataRicky Liang2015-05-201-1/+1
* clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao2015-05-061-0/+332
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