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path:
root
/
drivers
/
clk
/
mediatek
/
clk-pll.c
(
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Commit message (
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)
Author
Age
Files
Lines
*
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
Thomas Gleixner
2019-05-30
1
-9
/
+1
*
clk: mediatek: Allow changing PLL rate when it is off
James Liao
2019-04-11
1
-11
/
+2
*
clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data
Weiyi Lu
2019-04-11
1
-6
/
+11
*
clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
Owen Chen
2019-04-11
1
-4
/
+11
*
clk: mediatek: Disable tuner_en before change PLL rate
Owen Chen
2019-04-11
1
-14
/
+34
*
clk: mediatek: add the option for determining PLL source clock
Chen Zhong
2017-11-02
1
-1
/
+4
*
clk: mediatek: Add MT2712 clock support
weiyi.lu@mediatek.com
2017-11-02
1
-2
/
+11
*
clk: mediatek: Add MT2701 clock support
Shunli Wang
2016-11-09
1
-0
/
+1
*
clk: mediatek: remove __init from clk registration functions
James Liao
2016-08-19
1
-1
/
+1
*
clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS
James Liao
2015-10-01
1
-6
/
+1
*
clk: mediatek: Add MT8173 MMPLL change rate support
James Liao
2015-07-28
1
-3
/
+15
*
clk: mediatek: Fix calculation of PLL rate settings
James Liao
2015-07-28
1
-2
/
+2
*
clk: mediatek: Fix PLL registers setting flow
James Liao
2015-07-28
1
-9
/
+12
*
clk: mediatek: Initialize clk_init_data
Ricky Liang
2015-05-20
1
-1
/
+1
*
clk: mediatek: Add initial common clock support for Mediatek SoCs.
James Liao
2015-05-06
1
-0
/
+332