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path: root/drivers/clk/mediatek (follow)
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* clk/soc: mediatek: mt6779: Bind clock driver from platform deviceMatthias Brugger2020-05-201-7/+2
* clk/soc: mediatek: mt6797: Bind clock driver from platform deviceMatthias Brugger2020-05-201-7/+2
* clk/soc: mediatek: mt8183: Bind clock driver from platform deviceMatthias Brugger2020-05-201-7/+2
* clk / soc: mediatek: Bind clock and gpu driver for mt2701Enric Balletbo i Serra2020-05-201-7/+2
* clk / soc: mediatek: Bind clock and gpu driver for mt2712Enric Balletbo i Serra2020-05-201-7/+2
* clk / soc: mediatek: Move mt8173 MMSYS to platform driverMatthias Brugger2020-04-134-104/+154
* clk: Fix Kconfig indentationKrzysztof Kozlowski2020-01-051-22/+22
* clk: mediatek: mt6797: use devm_platform_ioremap_resource() to simplify codeYueHaibing2019-10-171-2/+1
* clk: mediatek: mt7629: use devm_platform_ioremap_resource() to simplify codeYueHaibing2019-10-171-4/+2
* clk: mediatek: mt7622: use devm_platform_ioremap_resource() to simplify codeYueHaibing2019-10-171-4/+2
* clk: mediatek: mt8183: use devm_platform_ioremap_resource() to simplify codeYueHaibing2019-10-171-4/+2
* clk: mediatek: mt6779: use devm_platform_ioremap_resource() to simplify codeYueHaibing2019-10-171-2/+1
* clk: mediatek: mt2712: use devm_platform_ioremap_resource() to simplify codeYueHaibing2019-10-171-4/+2
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-09-2118-11/+2102
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| * clk: mediatek: Runtime PM support for MT8183 mcucfg clock providerWeiyi Lu2019-09-171-2/+5
| * clk: mediatek: Register clock gate with deviceWeiyi Lu2019-09-174-6/+23
| * clk: mediatek: add pericfg clocks for MT8183Chunfeng Yun2019-09-171-0/+30
| * clk: mediatek: Add MT6779 clock supportmtk017612019-09-0911-0/+1974
| * clk: reset: Modify reset-controller driveryong.liang2019-08-083-4/+71
* | clk: mediatek: mt8183: Register 13MHz clock earlier for clocksourceWeiyi Lu2019-07-221-12/+34
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-175-24/+72
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| *-. Merge branches 'clk-debugfs', 'clk-unused', 'clk-refactor' and 'clk-qoriq' in...Stephen Boyd2019-07-121-5/+0
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| | | * clk: mediatek: mt8516: Remove unused variablePhilippe Mazenauer2019-06-071-5/+0
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| * | clk: mediatek: Remove MT8183 unused clockErin Lo2019-06-071-19/+0
| * | clk: mediatek: add audsys clock driver for MT8516Fabien Parent2019-06-073-0/+72
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* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner2019-05-3035-315/+35
* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
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*-. Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-...Stephen Boyd2019-05-0720-33/+3392
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| | * clk: mediatek: add clock driver for MT8516Fabien Parent2019-04-253-0/+824
| | * clk: mediatek: Allow changing PLL rate when it is offJames Liao2019-04-111-11/+2
| | * clk: mediatek: Add MT8183 clock supportWeiyi Lu2019-04-1115-0/+2196
| | * clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_dataWeiyi Lu2019-04-112-6/+12
| | * clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_dataOwen Chen2019-04-112-4/+13
| | * clk: mediatek: Add new clkmux register APIOwen Chen2019-04-113-1/+314
| | * clk: mediatek: Disable tuner_en before change PLL rateOwen Chen2019-04-111-14/+34
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* / clk: mediatek: fix clk-gate flag settingWeiyi Lu2019-04-121-2/+1
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*-. Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-roc...Stephen Boyd2019-03-081-2/+6
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| | * clk: mediatek: update clock driver of MT2712Weiyi Lu2019-02-051-2/+6
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*-----. \ Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk...Stephen Boyd2019-03-087-41/+75
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| | | | * clk: mediatek: correct cpu clock name for MT8173 SoCSeiya Wang2019-02-261-2/+2
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| | | * clk: mediatek: Mark bus and DRAM related clocks as criticalJasper Mattsson2019-02-261-25/+43
| | | * clk: mediatek: Add flags to mtk_gateJasper Mattsson2019-02-264-3/+7
| | | * clk: mediatek: Add MUX_FLAGS macroJasper Mattsson2019-02-261-2/+6
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| | * clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_selchunhui dai2019-02-251-2/+2
| | * clk: mediatek: add MUX_GATE_FLAGS_2chunhui dai2019-02-252-7/+15
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* / clk: mediatek: fix platform_no_drv_owner.cocci warningsYueHaibing2019-02-221-1/+0
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* clk: mediatek: fix the PCIe MAC clock parentRyder Lee2018-12-051-2/+2
* clk: mediatek: Drop more __init markings for driver probeStephen Boyd2018-11-301-2/+2
* clk: mediatek: Drop __init from mtk_clk_register_cpumuxes()Stephen Boyd2018-11-301-4/+4
* clk: mediatek: add clock support for MT7629 SoCRyder Lee2018-11-305-0/+1064
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 18:55:57 +0100