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path: root/drivers/clk/mediatek (follow)
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* treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-211-0/+1
*-. Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-...Stephen Boyd2019-05-0720-33/+3392
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| | * clk: mediatek: add clock driver for MT8516Fabien Parent2019-04-253-0/+824
| | * clk: mediatek: Allow changing PLL rate when it is offJames Liao2019-04-111-11/+2
| | * clk: mediatek: Add MT8183 clock supportWeiyi Lu2019-04-1115-0/+2196
| | * clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_dataWeiyi Lu2019-04-112-6/+12
| | * clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_dataOwen Chen2019-04-112-4/+13
| | * clk: mediatek: Add new clkmux register APIOwen Chen2019-04-113-1/+314
| | * clk: mediatek: Disable tuner_en before change PLL rateOwen Chen2019-04-111-14/+34
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* / clk: mediatek: fix clk-gate flag settingWeiyi Lu2019-04-121-2/+1
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*-. Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-roc...Stephen Boyd2019-03-081-2/+6
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| | * clk: mediatek: update clock driver of MT2712Weiyi Lu2019-02-051-2/+6
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*-----. \ Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk...Stephen Boyd2019-03-087-41/+75
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| | | | * clk: mediatek: correct cpu clock name for MT8173 SoCSeiya Wang2019-02-261-2/+2
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| | | * clk: mediatek: Mark bus and DRAM related clocks as criticalJasper Mattsson2019-02-261-25/+43
| | | * clk: mediatek: Add flags to mtk_gateJasper Mattsson2019-02-264-3/+7
| | | * clk: mediatek: Add MUX_FLAGS macroJasper Mattsson2019-02-261-2/+6
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| | * clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_selchunhui dai2019-02-251-2/+2
| | * clk: mediatek: add MUX_GATE_FLAGS_2chunhui dai2019-02-252-7/+15
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* / clk: mediatek: fix platform_no_drv_owner.cocci warningsYueHaibing2019-02-221-1/+0
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* clk: mediatek: fix the PCIe MAC clock parentRyder Lee2018-12-051-2/+2
* clk: mediatek: Drop more __init markings for driver probeStephen Boyd2018-11-301-2/+2
* clk: mediatek: Drop __init from mtk_clk_register_cpumuxes()Stephen Boyd2018-11-301-4/+4
* clk: mediatek: add clock support for MT7629 SoCRyder Lee2018-11-305-0/+1064
* clk: mediatek: remove unused array audio_parentsColin Ian King2018-08-311-5/+0
*-. Merge branches 'clk-hisi-usb', 'clk-silent-bulk', 'clk-mtk-hdmi', 'clk-mtk-ma...Stephen Boyd2018-06-044-2/+108
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| | * clk: mediatek: add g3dsys support for MT2701 and MT7623Sean Wang2018-05-163-0/+102
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| * clk: mediatek: correct the clocks for MT2701 HDMI PHY moduleRyder Lee2018-05-161-2/+6
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*-. Merge branches 'clk-mediatek', 'clk-hisi', 'clk-allwinner', 'clk-ux500' and '...Stephen Boyd2018-04-065-8/+215
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| * | clk: mediatek: add audsys support for MT2701Ryder Lee2018-03-203-0/+193
| * | clk: mediatek: add devm_of_platform_populate() for MT7622 audsysRyder Lee2018-03-201-1/+13
| * | clk: mediatek: update missing clock data for MT7622 audsysRyder Lee2018-03-191-0/+1
| * | clk: mediatek: fix PWM clock source by adding a fixed-factor clockSean Wang2018-03-191-7/+8
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* / clk: mediatek: update clock driver of MT2712Weiyi Lu2018-03-191-14/+55
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* clk: mediatek: adjust dependency of reset.c to avoid unexpectedly being builtSean Wang2018-01-103-9/+2
* clk: mediatek: Fix all warnings for missing struct clk_onecell_dataSean Wang2017-12-271-0/+1
* clk: mediatek: group drivers under indpendent menuSean Wang2017-12-221-46/+50
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2017-11-1817-4/+3520
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| * clk: mediatek: add clock support for MT7622 SoCSean Wang2017-11-026-0/+1334
| * clk: mediatek: add the option for determining PLL source clockChen Zhong2017-11-022-1/+5
| * clk: mediatek: mark mtk_infrasys_init_early __initArnd Bergmann2017-11-021-1/+1
| * clk: mediatek: Add MT2712 clock supportweiyi.lu@mediatek.com2017-11-0212-2/+2180
* | License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-021-0/+1
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* clk: Convert to using %pOF instead of full_nameRob Herring2017-07-223-3/+3
* clk: mediatek: fixed static checker warning in clk_cpumux_get_parent callSean Wang2017-07-181-4/+0
* clk: mediatek: export cpu multiplexer clock for MT8173 SoCsSean Wang2017-06-201-0/+23
* clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCsSean Wang2017-06-201-0/+8
* clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't workSean Wang2017-06-203-1/+151
* clk: mediatek: add mt2701 ethernet resetJohn Crispin2017-04-221-0/+2
* clk: mediatek: add clk support for MT6797Kevin-CW Chen2017-04-197-0/+1134
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