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path: root/drivers/clk/mediatek (follow)
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* clk: mediatek: remove hdmitx_dig_cts from TOP clocksPhilipp Zabel2016-05-061-1/+0
* clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock outputPhilipp Zabel2016-05-061-0/+5
* clk: mediatek: make dpi0_sel propagate rate changesPhilipp Zabel2016-05-062-3/+18
* clk: mediatek: Make reset_control_ops constPhilipp Zabel2016-03-301-1/+1
* clk: mediatek: Remove CLK_IS_ROOTStephen Boyd2016-03-031-2/+2
* clk: mediatek: Fix memory leak on clock init failJames Liao2016-01-291-2/+4
* clk: move the common clock's to_clk_*(_hw) macros to clk-provider.hGeliang Tang2016-01-292-5/+5
* clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao2015-10-015-7/+159
* clk: mediatek: Add subsystem clocks of MT8173James Liao2015-10-011-0/+267
* clk: mediatek: Fix rate and dependency of MT8173 clocksJames Liao2015-10-011-6/+13
* clk: mediatek: Add fixed clocks support for Mediatek SoC.James Liao2015-10-012-0/+40
* clk: mediatek: Add __initdata and __init for data and functionsJames Liao2015-10-013-10/+11
* clk: mediatek: Remove unused code from MT8173.James Liao2015-10-012-4/+2
* clk: mediatek: Removed unused dpi_ck clock from MT8173James Liao2015-10-011-1/+0
* clk: mediatek: add 13mhz clock for MT8173Joe.C2015-10-011-0/+5
* Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd2015-07-284-2/+6
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| * clk: mediatek: Properly include clk.hStephen Boyd2015-07-204-2/+6
* | clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao2015-07-283-6/+42
* | clk: mediatek: Fix calculation of PLL rate settingsJames Liao2015-07-281-2/+2
* | clk: mediatek: Fix PLL registers setting flowJames Liao2015-07-281-9/+12
* | clk: mediatek: mt8173: Fix enabling of critical clocksSascha Hauer2015-07-071-5/+21
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* clk: mediatek: Fix apmixedsys clock registrationJames Liao2015-06-042-2/+2
* clk: mediatek: Initialize clk_init_dataRicky Liang2015-05-202-2/+2
* clk: mediatek: Add basic clocks for Mediatek MT8173.James Liao2015-05-062-0/+831
* clk: mediatek: Add basic clocks for Mediatek MT8135.James Liao2015-05-062-0/+645
* clk: mediatek: Add reset controller supportSascha Hauer2015-05-063-0/+108
* clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao2015-05-066-0/+898
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