| Commit message (Collapse) | Author | Age | Files | Lines |
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Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
$ sed -e 's/^ /\t/' -i */Kconfig
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lkml.kernel.org/r/1574306335-29026-1-git-send-email-krzk@kernel.org
[sboyd@kernel.org: Fixup mediatek to have two spaces for help indent]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015124728.25072-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015124226.25792-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015121735.26228-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015121421.26144-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015121035.24736-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015112644.19816-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We have a small collection of core framework updates this time, mostly
around clk registration by clk providers and debugfs "nice to haves"
for rate constraints. I'll highlight that we're now setting the
clk_init_data pointer inside struct clk_hw to NULL during
clk_register(), which may break some drivers that thought they could
use that pointer during normal operations. That change has been
sitting in next for a while now but maybe something is still broken.
We'l see. Other than that the core framework changes aren't invasive
and they're fixing bugs, simplifying, and making things better.
On the clk driver side we got the usual addition of new SoC support,
new features for existing drivers, and bug fixes scattered throughout.
The biggest diffstat is the Amlogic driver that gained CPU clk support
in addition to migrating to the new way of specifying clk parents.
After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got
support for various new SoCs and clock controllers from those vendors.
Core:
- Drop NULL checks in clk debugfs
- Add min/max rates to clk debugfs
- Set clk_init_data pointer inside clk_hw to NULL after registration
- Make clk_bulk_get_all() return an 'id' corresponding to clock-names
- Evict parents from parent cache when they're unregistered
New Drivers:
- Add clock driver for i.MX8MN SoCs
- Support aspeed AST2600 SoCs
- Support for Mediatek MT6779 SoCs
- Support qcom SM8150 GCC and RPMh clks
- Support qcom QCS404 WCSS clks
- Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
- Addition of clock driver for Rockchip rk3308 SoCs
Updates:
- Add regulator support to the cdce925 clk driver
- Add support for Raspberry Pi 4 bcm2711 SoCs
- Add SDIO gate support to aspeed driver
- Add missing of_node_put() calls in various clk drivers
- Migrate Amlogic driver to new clock parent description method
- Add DVFS support to Amlogic Meson g12
- Add Amlogic Meson g12a reset support to the axg audio clock controller
- Add sm1 support to the Amlogic Meson g12a clock controller
- Switch i.MX8MM clock driver to platform driver
- Add Hifi4 DSP related clocks for i.MX8QXP SoC
- Fix Audio PLL setting and parent clock for USB
- Misc i.MX8 clock driver improvements and corrections
- Set floor ops for Qualcomm SD clks so that rounding works
- Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1
- Enable the Allwinner V3 SoC and fix the i2s clock for H6"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits)
clk: Drop !clk checks in debugfs dumping
clk: imx: imx8mn: fix pll mux bit
clk: imx: imx8mm: fix pll mux bit
clk: imx: clk-pll14xx: unbypass PLL by default
clk: imx: pll14xx: avoid glitch when set rate
clk: mvebu: ap80x: add AP807 clock support
clk: mvebu: ap806: Prepare the introduction of AP807 clock support
clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
clk: mvebu: ap806: be more explicit on what SaR is
clk: mvebu: ap80x-cpu: add AP807 CPU clock support
clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
dt-bindings: ap806: Document AP807 clock compatible
dt-bindings: ap80x: Document AP807 CPU clock compatible
clk: sprd: add missing kfree
clk: at91: allow 24 Mhz clock as input for PLL
clk: Make clk_bulk_get_all() return a valid "id"
clk: actions: Fix factor clk struct member access
clk: qcom: rcg: Return failure for RCG update
clk: remove extra ---help--- tags in Kconfig
clk: add include guard to clk-conf.h
...
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Enable the runtime PM support and forward the struct device pointer for
registration of MT8183 mcucfg clocks.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Link: https://lkml.kernel.org/r/1567414859-3244-3-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Allow those clocks under a power domain to do the runtime pm operation
by forwarding the struct device pointer from clock provider.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Link: https://lkml.kernel.org/r/1567414859-3244-2-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add pericfg clocks for MT8183, it's used when support USB
remote wakeup
Cc: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lkml.kernel.org/r/1566980533-28282-2-git-send-email-chunfeng.yun@mediatek.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add MT6779 clock support, include topckgen, apmixedsys,
infracfg, and subsystem clocks.
Signed-off-by: mtk01761 <wendell.lin@mediatek.com>
Link: https://lkml.kernel.org/r/1566206502-4347-11-git-send-email-mars.cheng@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Set reset signal by a register and
clear reset signal by another register for 8183.
Signed-off-by: yong.liang <yong.liang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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The 13MHz clock should be registered before clocksource driver is
initialized. Use CLK_OF_DECLARE_DRIVER() to guarantee.
Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support")
Cc: <stable@vger.kernel.org>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This round of clk driver and framework updates is heavy on the driver
update side. The two main highlights in the core framework are the
addition of an bulk clk_get API that handles optional clks and an
extra debugfs file that tells the developer about the current parent
of a clk.
The driver updates are dominated by i.MX in the diffstat, but that is
mostly because that SoC has started converting to the clk_hw style of
clk registration. The next big update is in the Amlogic meson clk
driver that gained some support for audio, cpu, and temperature clks
while fixing some PLL issues. Finally, the biggest thing that stands
out is the conversion of a large part of the Allwinner sunxi-ng driver
to the new clk parent scheme that uses less strings and more pointer
comparisons to match clk parents and children up.
In general, it looks like we have a lot of little fixes and tweaks
here and there to clk data along with the normal addition of a handful
of new drivers and a couple new core framework features.
Core:
- Add a 'clk_parent' file in clk debugfs
- Add a clk_bulk_get_optional() API (with devm too)
New Drivers:
- Support gated clk controller on MIPS based BCM63XX SoCs
- Support SiLabs Si5341 and Si5340 chips
- Support for CPU clks on Raspberry Pi devices
- Audsys clock driver for MediaTek MT8516 SoCs
Updates:
- Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
- Small frequency support for SiLabs Si544 chips
- Slow clk support for AT91 SAM9X60 SoCs
- Remove dead code in various clk drivers (-Wunused)
- Support for Marvell 98DX1135 SoCs
- Get duty cycle of generic pwm clks
- Improvement in mmc phase calculation and cleanup of some rate defintions
- Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
- Add clks for new Exynos5422 Dynamic Memory Controller driver
- Clock definition for Exynos4412 Mali
- Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
- Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
- TI clock probing done from DT by default instead of firmware
- Fix Amlogic Meson mpll fractional part and spread sprectrum issues
- Add Amlogic meson8 audio clocks
- Add Amlogic g12a temperature sensors clocks
- Add Amlogic g12a and g12b cpu clocks
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
- Add Clock Domain support on Renesas RZ/N1"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits)
clk: consoldiate the __clk_get_hw() declarations
clk: sprd: Add check for return value of sprd_clk_regmap_init()
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
clk: Add Si5341/Si5340 driver
dt-bindings: clock: Add silabs,si5341
clk: clk-si544: Implement small frequency change support
clk: add BCM63XX gated clock controller driver
devicetree: document the BCM63XX gated clock bindings
clk: at91: sckc: use dedicated functions to unregister clock
clk: at91: sckc: improve error path for sama5d4 sck registration
clk: at91: sckc: remove unnecessary line
clk: at91: sckc: improve error path for sam9x5 sck register
clk: at91: sckc: add support to free slow clock osclillator
clk: at91: sckc: add support to free slow rc oscillator
clk: at91: sckc: add support to free slow oscillator
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: at91: sckc: add support for SAM9X60
...
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into clk-next
- Add a 'clk_parent' file in clk debugfs
- Remove dead code in various clk drivers
* clk-debugfs:
clk: Add clk_parent entry in debugfs
* clk-unused:
clk: qcom: Fix -Wunused-const-variable
clk: mmp: frac: Remove set but not used variable 'prev_rate'
clk: ti: Remove unused functions
clk: mediatek: mt8516: Remove unused variable
* clk-refactor:
clk: clk-cdce706: simplify getting the adapter of a client
clk: Simplify clk_core_can_round()
* clk-qoriq:
clk: qoriq: add support for lx2160a
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Variable 'ddrphycfg_parents' is defined static and initialized, but not
used in the file.
../drivers/clk/mediatek/clk-mt8516.c:234:27: warning: ‘ddrphycfg_parents’ defined but not used [-Wunused-const-variable=]
static const char * const ddrphycfg_parents[] __initconst = {
^~~~~~~~~~~~~~~~~
Signed-off-by: Philippe Mazenauer <philippe.mazenauer@outlook.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Remove MT8183 sspm clock
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add audsys clock driver for MediaTek MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Based on 1 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation this program is
distributed in the hope that it will be useful but without any
warranty without even the implied warranty of merchantability or
fitness for a particular purpose see the gnu general public license
for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 655 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:
GPL-2.0-only
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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'clk-imx' into clk-next
- Qualcomm QCS404 CDSP clk support
- Qualcomm QCS404 Turing clk support
- Mediatek MT8183 clock support
- Mediatek MT8516 clock support
- Milbeaut M10V clk controller support
* clk-renesas:
clk: renesas: rcar-gen3: Remove unused variable
clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value
clk: renesas: r8a77980: Fix RPC-IF module clock's parent
clk: renesas: rcar-gen3: Rename DRIF clocks
clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
clk: renesas: rcar-gen3: Correct parent clock of HS-USB
clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
clk: renesas: r8a774c0: Add Z2 clock
clk: renesas: r8a77990: Add Z2 clock
clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents
math64: New DIV64_U64_ROUND_CLOSEST helper
clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
clk: renesas: r9a06g032: Add missing PCI USB clock
clk: renesas: r7s9210: Always use readl()
clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()
* clk-qcom:
clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998
clk: qcom: Add QCS404 TuringCC
clk: qcom: branch: Add AON clock ops
dt-bindings: clock: Introduce Qualcomm Turing Clock controller
clk: qcom: gcc-qcs404: Add CDSP related clocks and resets
* clk-mtk:
clk: mediatek: add clock driver for MT8516
dt-bindings: mediatek: apmixedsys: add support for MT8516
dt-bindings: mediatek: infracfg: add support for MT8516
dt-bindings: mediatek: topckgen: add support for MT8516
clk: mediatek: Allow changing PLL rate when it is off
clk: mediatek: Add MT8183 clock support
clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data
clk: mediatek: Add dt-bindings for MT8183 clocks
dt-bindings: ARM: Mediatek: Document bindings for MT8183
clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
clk: mediatek: Add new clkmux register API
clk: mediatek: Disable tuner_en before change PLL rate
* clk-milbeaut:
clock: milbeaut: Add Milbeaut M10V clock controller
dt-bindings: clock: milbeaut: add Milbeaut clock description
* clk-imx:
clk: imx: correct pfdv2 gate_bit/vld_bit operations
clk: imx: clk-pllv3: mark expected switch fall-throughs
clk: imx8mq: Add dsi_ipg_div
clk: imx: pllv4: add fractional-N pll support
clk: imx: keep uart clock on during system boot
clk: imx: correct i.MX7D AV PLL num/denom offset
clk: imx6sll: Fix mispelling uart4_serial as serail
clk: imx: pll14xx: drop unused variable
clk: imx: rename clk-imx51-imx53.c to clk-imx5.c
clk: imx5: Fix i.MX50 ESDHC clock registers
clk: imx5: Fix i.MX50 mainbus clock registers
clk: imx: Remove unused imx_get_clk_hw_fixed
dt-bindings: clock: imx7ulp: remove SNVS clock
clk: imx7ulp: remove snvs clock
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Add the clock driver for the MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Some modules may need to change its clock rate before turn on it.
So changing PLL's rate when it is off should be allowed.
This patch removes PLL enabled check before set rate, so that
PLLs can set new frequency even if they are off.
On MT8173 for example, ARMPLL's enable bit can be controlled by
other HW. That means ARMPLL may be turned on even if we (CPU / SW)
set ARMPLL's enable bit as 0. In this case, SW may want and can
still change ARMPLL's rate by changing its pcw and postdiv settings.
But without this patch, new pcw setting will not be applied because
its enable bit is 0.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Michael Turquette <mturuqette@baylibre.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add MT8183 clock support, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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In previous MediaTek PLL design, it assumes the pcw change control
is always on the CON1 register.
However, the pcw change bit on MT8183 was moved onto CON0 because
the the PCW length of audio PLLs are extended to 32-bit.
Add configurable pcw_chg_reg to set the pcw change control register
address or using the default control register CON1 if without
setting in pll data.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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1. pcwibits: The integer bits of pcw for PLLs is extend to 8 bits,
add a variable to indicate this change and
backward-compatible.
2. fmin: The PLL frequency lower-bound is vary from 1GHz to
1.5GHz, add a variable to indicate platform-dependent.
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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On both MT8183 & MT6765, there add "set/clr" register for
each clkmux setting, and one update register to trigger value change.
It is designed to prevent read-modify-write racing issue.
The sw design need to add a new API to handle this hw change with
a new mtk_clk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
[sboyd@kernel.org: Squash in flags=0 to silence warning]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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PLLs with tuner_en bit, such as APLL1, need to disable
tuner_en before apply new frequency settings, or the new frequency
settings (pcw) will not be applied.
The tuner_en bit will be disabled during changing PLL rate
and be restored after new settings applied.
Fixes: e2f744a82d725 (clk: mediatek: Add MT2712 clock support)
Cc: <stable@vger.kernel.org>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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CLK_SET_RATE_PARENT would be dropped.
Merge two flag setting together to correct the error.
Fixes: 5a1cc4c27ad2 ("clk: mediatek: Add flags to mtk_gate")
Cc: <stable@vger.kernel.org>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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'clk-rockchip' into clk-next
- Convert a few clk bindings to JSON schema format
- 3rd ECO fix for Mediatek MT2712 SoCs
* clk-typo:
clk: samsung: fix typo
* clk-json-schema:
dt-bindings: clock: Convert fixed-factor-clock to json-schema
dt-bindings: clock: Convert fixed-clock binding to json-schema
* clk-mtk-2712-eco:
clk: mediatek: update clock driver of MT2712
dt-bindings: clock: add clock for MT2712
* clk-rockchip:
clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks
clk: rockchip: fix frac settings of GPLL clock for rk3328
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According to 3rd ECO design change,
1. Add new fixed factor clock of audio.
2. Add the parent clocks for audio clock mux.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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'clk-mtk-crit' and 'clk-mtk' into clk-next
* clk-ingenic:
clk: ingenic: Remove set but not used variable 'enable'
clk: ingenic: Fix doc of ingenic_cgu_div_info
clk: ingenic: Fix round_rate misbehaving with non-integer dividers
clk: ingenic: jz4740: Fix gating of UDC clock
* clk-mtk-mux:
clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
clk: mediatek: add MUX_GATE_FLAGS_2
* clk-qcom-sdm845-pcie:
clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks
* clk-mtk-crit:
clk: mediatek: Mark bus and DRAM related clocks as critical
clk: mediatek: Add flags to mtk_gate
clk: mediatek: Add MUX_FLAGS macro
* clk-mtk:
clk: mediatek: correct cpu clock name for MT8173 SoC
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Correct cpu clock name from ca57 to ca72 since MT8173 does use cortex-a72.
Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Currently, DRAM-related clocks are not marked with CLK_IS_CRITICAL
for MT6797. This causes memory corruption when the system is
booted without clk_ignore_unused.
This patch marks MUX ddrphycfg_sel as well as gates infra_dramc_f26m
and infra_dramc_b_f26m as CLK_IS_CRITICAL.
Signed-off-by: Jasper Mattsson <jasu@njomotys.info>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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This is required to mark gates as CLK_IS_CRITICAL.
Signed-off-by: Jasper Mattsson <jasu@njomotys.info>
Acked-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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This is required to mark outputs of certain MUXes as CLK_IS_CRITICAL.
Signed-off-by: Jasper Mattsson <jasu@njomotys.info>
Acked-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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The MUX clock of dpi1_sel should select the closet clock for itself.
We could add this flag to enable this function of MUX in CCF.
Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
Signed-off-by: wangyan wang <wangyan.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add MUX_GATE_FLAGS_2 for the clock which needs to set two falgs.
Such as some mux need to set the flags of "CLK_MUX_ROUND_CLOSEST".
Signed-off-by: chunhui dai <chunhui.dai@mediatek.com>
Signed-off-by: wangyan wang <wangyan.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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The PCIe function doesn't work as the clock tree of MAC layer is wrong.
Hence fix the clock table.
Fixes: 3b5e748615e7 ("clk: mediatek: add clock support for MT7629 SoC")
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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This function is called from driver probe, which isn't the same as
__init code because driver probe can happen later. Drop the __init
marking here to fix this potential problem.
Cc: Sean Wang <sean.wang@mediatek.com>
Cc: Ryder Lee <ryder.lee@mediatek.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Wenzhen Yu <wenzhen.yu@mediatek.com>
Cc: Weiyi Lu <weiyi.lu@mediatek.com>
Fixes: 2fc0a509e4ee ("clk: mediatek: add clock support for MT7622 SoC")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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This function is used from more places than just __init code. Removing
__init silences a section mismatch warning here.
Cc: Sean Wang <sean.wang@mediatek.com>
Cc: Ryder Lee <ryder.lee@mediatek.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Wenzhen Yu <wenzhen.yu@mediatek.com>
Cc: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Add all supported clocks exported from every susbystem found on MT7629 SoC.
Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Array audio_parents is declared but never used, hence it is redundant
and can be removed.
Cleans up clang warning:
warning: 'audio_parents' defined but not used [-Wunused-const-variable=]
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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'clk-mtk-mali' and 'clk-imx6ul-ccosr' into clk-next
* clk-hisi-usb:
clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC
* clk-silent-bulk:
clk: bulk: silently error out on EPROBE_DEFER
* clk-mtk-hdmi:
clk: mediatek: correct the clocks for MT2701 HDMI PHY module
* clk-mtk-mali:
clk: mediatek: add g3dsys support for MT2701 and MT7623
dt-bindings: reset: mediatek: add entry for Mali-450 node to refer
dt-bindings: clock: mediatek: add entry for Mali-450 node to refer
dt-bindings: clock: mediatek: add g3dsys bindings
* clk-imx6ul-ccosr:
clk: imx: Add new clo01 and clo2 controlled by CCOSR
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Add clock driver support for g3dsys on MT2701 and MT7623, which is
providing essential clock gate and reset controller to Mali-450.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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The hdmitx_dig_cts clock signal is not a child of clk26m,
and the actual output of the PLL block is derived from
the tvdpll via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.
Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
Signed-off-by: Chunhui Dai <chunhui.dai@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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'clk-renesas' into clk-next
* clk-mediatek:
clk: mediatek: add audsys support for MT2701
clk: mediatek: add devm_of_platform_populate() for MT7622 audsys
dt-bindings: clock: mediatek: add audsys support for MT2701
dt-bindings: clock: mediatek: update audsys documentation to adapt MFD device
clk: mediatek: update missing clock data for MT7622 audsys
clk: mediatek: fix PWM clock source by adding a fixed-factor clock
dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4
* clk-hisi:
clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc()
clk: hisilicon: mark wdt_mux_p[] as const
clk: hisilicon: Mark phase_ops static
clk: hi3798cv200: add emmc sample and drive clock
clk: hisilicon: add hisi phase clock support
clk: hi3798cv200: add COMBPHY0 clock support
clk: hi3798cv200: fix define indentation
clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK
clk: hi3798cv200: correct IR clock parent
clk: hi3798cv200: fix unregister call sequence in error path
* clk-allwinner:
clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
clk: sunxi-ng: add support for the Allwinner H6 CCU
dt-bindings: add device tree binding for Allwinner H6 main CCU
clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate
clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
clk: sunxi-ng: Add check for minimal rate to NM PLLs
clk: sunxi-ng: Use u64 for calculation of nkmp rate
clk: sunxi-ng: Mask nkmp factors when setting register
clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name
* clk-ux500:
clk: ux500: Drop AB8540/9540 support
* clk-renesas: (27 commits)
clk: renesas: cpg-mssr: Adjust r8a77980 ifdef
clk: renesas: rcar-gen3: Always use readl()/writel()
clk: renesas: sh73a0: Always use readl()/writel()
clk: renesas: rza1: Always use readl()/writel()
clk: renesas: rcar-gen2: Always use readl()/writel()
clk: renesas: r8a7740: Always use readl()/writel()
clk: renesas: r8a73a4: Always use readl()/writel()
clk: renesas: mstp: Always use readl()/writel()
clk: renesas: div6: Always use readl()/writel()
clk: fix false-positive Wmaybe-uninitialized warning
clk: renesas: r8a77965: Replace DU2 clock
clk: renesas: cpg-mssr: Add support for R-Car M3-N
clk: renesas: cpg-mssr: add R8A77980 support
dt-bindings: clock: add R8A77980 CPG core clock definitions
clk: renesas: r8a7792: Add rwdt clock
clk: renesas: r8a7794: Add rwdt clock
clk: renesas: r8a7791/r8a7793: Add rwdt clock
clk: renesas: r8a7790: Add rwdt clock
clk: renesas: r8a7745: Add rwdt clock
clk: renesas: r8a7743: Add rwdt clock
...
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Add clock driver support for MT2701 audsys.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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