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* clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.cRan Jianping2021-11-021-2/+0
| | | | | | | | | | | | 'dt-bindings/clock/mt8195-clk.h' included in '/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c' is duplicated.It is also included on the 13 line. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Ran Jianping <ran.jianping@zte.com.cn> Link: https://lore.kernel.org/r/20211019062939.979660-1-ran.jianping@zte.com.cn Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Export clk_ops structures to modulesStephen Boyd2021-09-151-0/+2
| | | | | | | | | | | | | | | | modpost complains once these drivers become modules. ERROR: modpost: "mtk_mux_gate_clr_set_upd_ops" [drivers/clk/mediatek/clk-mt6779.ko] undefined! Let's just export them. Cc: Hanks Chen <hanks.chen@mediatek.com> Cc: Wendell Lin <wendell.lin@mediatek.com> Cc: Lee Jones <lee.jones@linaro.org> Cc: Miles Chen <miles.chen@mediatek.com> Fixes: 32b028fb1d09 ("clk: mediatek: support COMMON_CLK_MEDIATEK module build") Link: https://lore.kernel.org/r/20210915015540.1732014-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: support COMMON_CLK_MT6779 module buildMiles Chen2021-09-1510-17/+35
| | | | | | | | | | | | | To support COMMON_CLK_MT6779* module build, add MODULE_LICENSE and export necessary symbols. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Hanks Chen <hanks.chen@mediatek.com> Cc: Wendell Lin <wendell.lin@mediatek.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20210901222526.31065-4-miles.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: support COMMON_CLK_MEDIATEK module buildMiles Chen2021-09-158-1/+33
| | | | | | | | | | | | | To support COMMON_CLK_MEDIATEK module build, add MODULE_LICENSE and export necessary symbols. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Hanks Chen <hanks.chen@mediatek.com> Cc: Wendell Lin <wendell.lin@mediatek.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20210901222526.31065-3-miles.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 apusys clock supportChun-Jie Chen2021-09-152-1/+94
| | | | | | | | | | Add MT8195 apusys clock controller which provides PLLs in AI processor Unit. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-25-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 imp i2c wrapper clock supportChun-Jie Chen2021-09-152-1/+69
| | | | | | | | | | Add MT8195 imp i2c wrapper clock controllers which provide clock gate control in I2C IP blocks. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-24-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 wpesys clock supportChun-Jie Chen2021-09-152-1/+145
| | | | | | | | | Add MT8195 wpesys clock controllers which provide clock gate control in Wrapping Engine. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-23-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 vppsys1 clock supportChun-Jie Chen2021-09-152-1/+109
| | | | | | | | | | Add MT8195 vppsys1 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-22-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 vppsys0 clock supportChun-Jie Chen2021-09-152-1/+111
| | | | | | | | | | Add MT8195 vppsys0 clock controller which provides clock gate controller for Video Processor Pipe. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-21-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 vencsys clock supportChun-Jie Chen2021-09-152-1/+71
| | | | | | | | | Add MT8195 vencsys clock controllers which provide clock gate control for video encoder. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-20-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 vdosys1 clock supportChun-Jie Chen2021-09-152-1/+141
| | | | | | | | | | | | Add MT8195 vdosys1 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-19-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 vdosys0 clock supportChun-Jie Chen2021-09-152-1/+124
| | | | | | | | | | | | Add MT8195 vdosys0 clock controller which provides clock gate control in video system. This is integrated with mtk-mmsys driver which will populate device by platform_device_register_data to start vdosys clock driver. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-18-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 vdecsys clock supportChun-Jie Chen2021-09-152-1/+106
| | | | | | | | | | Add MT8195 vdec clock controllers which provide clock gate control for video decoder. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-17-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 scp adsp clock supportChun-Jie Chen2021-09-152-1/+48
| | | | | | | | | | Add MT8195 scp adsp clock controller which provides clock gate control for Audio DSP. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-16-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 mfgcfg clock supportChun-Jie Chen2021-09-152-1/+48
| | | | | | | | | | Add MT8195 mfg clock controller which provides clock gate control for GPU. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-15-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 ipesys clock supportChun-Jie Chen2021-09-152-1/+53
| | | | | | | | | | Add MT8195 ipesys clock controller which provides clock gate control for Image Process Engine. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-14-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 imgsys clock supportChun-Jie Chen2021-09-152-1/+97
| | | | | | | | | | Add MT8195 imgsys clock controllers which provide clock gate control for image IP blocks. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-13-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 ccusys clock supportChun-Jie Chen2021-09-152-1/+51
| | | | | | | | | | Add MT8195 ccusys clock controller which provides clock gate control in Camera Computing Unit. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-12-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 camsys clock supportChun-Jie Chen2021-09-152-1/+144
| | | | | | | | | | Add MT8195 camsys clock controllers which provide clock gate control for camera IP blocks. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-11-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 infrastructure clock supportChun-Jie Chen2021-09-152-1/+207
| | | | | | | | | | Add MT8195 infrastructure clock controller which provides clock gate control for basic IP like pwm, uart, spi and so on. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-10-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 peripheral clock supportChun-Jie Chen2021-09-152-1/+64
| | | | | | | | | | Add MT8195 peripheral clock controller which provides clock gate control for ethernet/flashif/pcie/ssusb. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-9-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 topckgen clock supportChun-Jie Chen2021-09-152-1/+1274
| | | | | | | | | | Add MT8195 topckgen clock controller which provides muxes, dividers to handle variety clock selection in other IP blocks. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210914021633.26377-8-chun-jie.chen@mediatek.com Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8195 apmixedsys clock supportChun-Jie Chen2021-09-153-0/+154
| | | | | | | | | | Add MT8195 apmixedsys clock controller which provides Plls generated from SoC 26m and ssusb clock gate control. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-7-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Fix resource leak in mtk_clk_simple_probeChun-Jie Chen2021-09-151-2/+10
| | | | | | | | | | Release clock data when clock driver probe fail to fix possible resource leak. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-6-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add API for clock resource recycleChun-Jie Chen2021-09-152-0/+10
| | | | | | | | | | In order to avoid resource leak when fail clock registration appears, so adds the common interface to handle it. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-5-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Fix corner case of tuner_en_regChun-Jie Chen2021-09-151-1/+1
| | | | | | | | | | | | | On MT8195, tuner_en_reg is moved to register offest 0x0. If we only judge by tuner_en_reg, it may lead to wrong address. Add tuner_en_bit to the check condition. And it has been confirmed, on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by clock square control. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20210914021633.26377-4-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167Miles Chen2021-07-271-15/+10
| | | | | | | | | | | | | | | | I found that COMMON_CLK_MT8167* do not depend on COMMON_CLK_MT8167, so it is possible to config: CONFIG_COMMON_CLK_MT8167=n CONFIG_COMMON_CLK_MT8167_*=y Although it does not cause build breaks with such configuration, I think it is clearer to make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167. Signed-off-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20210716051732.3422-1-miles.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 vencsys clock supportChun-Jie Chen2021-07-273-0/+60
| | | | | | | | | | Add MT8192 vencsys clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-22-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 vdecsys clock supportChun-Jie Chen2021-07-273-0/+101
| | | | | | | | | | Add MT8192 vdecsys and vdecsys soc clock providers Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-21-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 scp adsp clock supportChun-Jie Chen2021-07-273-0/+57
| | | | | | | | | | Add MT8192 scp adsp clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-20-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 msdc clock supportChun-Jie Chen2021-07-273-0/+92
| | | | | | | | | | Add MT8192 msdc and msdc top clock providers Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-19-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 mmsys clock supportChun-Jie Chen2021-07-273-0/+115
| | | | | | | | | | Add MT8192 mmsys clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20210726105719.15793-18-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 mfgcfg clock supportChun-Jie Chen2021-07-273-0/+57
| | | | | | | | | | Add MT8192 mfgcfg clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-17-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 mdpsys clock supportChun-Jie Chen2021-07-273-0/+89
| | | | | | | | | | Add MT8192 mdpsys clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-16-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 ipesys clock supportChun-Jie Chen2021-07-273-0/+64
| | | | | | | | | | Add MT8192 ipesys clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-15-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 imp i2c wrapper clock supportChun-Jie Chen2021-07-273-0/+126
| | | | | | | | | | Add MT8192 imp i2c wrapper clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-14-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 imgsys clock supportChun-Jie Chen2021-07-273-0/+77
| | | | | | | | | | Add MT8192 imgsys and imgsys2 clock providers Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-13-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 camsys clock supportChun-Jie Chen2021-07-273-0/+114
| | | | | | | | | | Add MT8192 camsys and camsys raw clock providers Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-12-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 audio clock supportChun-Jie Chen2021-07-273-0/+125
| | | | | | | | | | Add MT8192 audio clock provider Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-11-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add MT8192 basic clocks supportChun-Jie Chen2021-07-275-4/+1358
| | | | | | | | | | | Add MT8192 basic clock providers, include topckgen, apmixedsys, infracfg and pericfg. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-10-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providersChun-Jie Chen2021-07-272-0/+31
| | | | | | | | | | | | Most of subsystem clock providers only need to register clock gates in their probe() function. To reduce the duplicated code by add a generic function. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-9-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Add configurable enable control to mtk_pll_dataChun-Jie Chen2021-07-272-14/+21
| | | | | | | | | | | | | | | | | | In all MediaTek PLL design, bit0 of CON0 register is always the enable bit. However, there's a special case of usbpll on MT8192. The enable bit of usbpll is moved to bit2 of other register. Add configurable en_reg and pll_en_bit for enable control or default 0 where pll data are static variables. Hence, CON0_BASE_EN could also be removed. And there might have another special case on other chips, the enable bit is still on CON0 register but not at bit0. Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-8-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Fix asymmetrical PLL enable and disable controlChun-Jie Chen2021-07-271-4/+16
| | | | | | | | | | | | | | | | | | | | In fact, the en_mask is a combination of divider enable mask and pll enable bit(bit0). Before this patch, we enabled both divider mask and bit0 in prepare(), but only cleared the bit0 in unprepare(). In the future, we hope en_mask will only be used as divider enable mask. The enable register(CON0) will be set in 2 steps: first is divider mask, and then bit0 during prepare(), and vice versa. But considering backward compatibility, at this stage we allow en_mask to be a combination or a pure divider enable mask. And then we will make en_mask a pure divider enable mask in another following patch series. Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-7-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Get regmap without syscon compatible checkChun-Jie Chen2021-07-274-4/+4
| | | | | | | | | | | Not all clock providers need to be marked compatible with "syscon" for system configuration usage, so use device_node_to_regmap() to skip "syscon" check. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-6-chun-jie.chen@mediatek.com Reviewed-by: Ikjoon Jang <ikjn@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: mux: Update parent at enable timeLaurent Pinchart2021-02-092-3/+30
| | | | | | | | | | | The mux clocks don't always correctly take the new parent into account when the parent is updated while the clock is disabled. Set the update bit when enabling the clock to force an update of the mux. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210125170819.26130-3-laurent.pinchart@ideasonboard.com Reviewed-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: mux: Drop unused clock opsLaurent Pinchart2021-02-092-70/+4
| | | | | | | | Three out of the four defined clock ops are unused. Drop them. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210125170819.26130-2-laurent.pinchart@ideasonboard.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Select all the MT8183 clocks by defaultEnric Balletbo i Serra2021-02-091-0/+11
| | | | | | | | | | | | | | | If MT8183 SoC support is enabled, almost all machines will use topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks, so it feels wrong to require each one to select that symbols manually. Instead, enable it whenever COMMON_CLK_MT8183_* is disabled as a simplification. This would add few KB in the kernel image size but will make the life a bit easier to the users, anyway you'll need to probably enable all of them if you want to have proper support for that SoC. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20210203105423.682960-1-enric.balletbo@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: mediatek: Make mtk_clk_register_mux() a static functionWeiyi Lu2020-12-172-5/+1
| | | | | | | | | mtk_clk_register_mux() should be a static function Fixes: a3ae549917f16 ("clk: mediatek: Add new clkmux register API") Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Link: https://lore.kernel.org/r/1605256192-31307-1-git-send-email-weiyi.lu@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
*-. Merge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and ↵Stephen Boyd2020-10-2012-14/+1511
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-mediatek' into clk-next - Small non-critical fixes for TI clk driver - Support Mediatek MT8167 clks * clk-simplify: clk: mediatek: fix platform_no_drv_owner.cocci warnings clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_init clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_init * clk-ti: clk: ti: dra7: add missing clkctrl register for SHA2 instance clk: ti: clockdomain: fix static checker warning clk: ti: autoidle: add checks against NULL pointer reference clk: keystone: sci-clk: add 10% slack to set_rate clk: keystone: sci-clk: cache results of last query rate operation clk: keystone: sci-clk: fix parsing assigned-clock data during probe * clk-tegra: clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate() * clk-rockchip: clk: rockchip: Initialize hw to error to avoid undefined behavior clk: rockchip: rk3399: Support module build clk: rockchip: fix the clk config to support module build clk: rockchip: Export some clock common APIs for module drivers clk: rockchip: Export rockchip_register_softrst() clk: rockchip: Export rockchip_clk_register_ddrclk() clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls clk: rockchip: rk3308: drop unused mux_timer_src_p * clk-mediatek: clk: mediatek: Add MT8167 clock support dt-bindings: clock: mediatek: add bindings for MT8167 clocks clk: mediatek: add UART0 clock support
| | * clk: mediatek: Add MT8167 clock supportFabien Parent2020-10-148-0/+1505
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the following clock support for MT8167 SoC: topckgen, apmixedsys, infracfg, audsys, imgsys, mfgcfg, vdecsys. Signed-off-by: Fabien Parent <fparent@baylibre.com> Link: https://lore.kernel.org/r/20200918132303.2831815-2-fparent@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-18 11:44:42 +0100