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* clk: meson: Add G12A AO Clock + Reset ControllerNeil Armstrong2019-02-131-0/+2
| | | | | | | | | | | | | Add the Amlogic G12A AO Clock and Reset controller driver handling generation of Always-On clocks : - AO Clocks and Reset for Always-On modules - 32K Generation for USB and CEC - SAR ADC controller clock Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190212162859.20743-3-narmstrong@baylibre.com
* clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet2019-02-041-3/+8
| | | | | | | | | | | The function used to probe the peripheral clock controller of the arm64 amlogic SoCs is mostly the same. We now have 3 of those controllers so it is time to factorize things a bit. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-5-jbrunet@baylibre.com
* clk: meson: g12a: add peripheral clock controllerJian Hu2019-02-041-0/+12
| | | | | | | | | | Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com
* clk: meson: rework and clean drivers dependenciesJerome Brunet2019-02-021-24/+58
| | | | | | | | | | | | | | | | | | | | | | | Initially, the meson clock directory only hosted 2 controllers drivers, for meson8 and gxbb. At the time, both used the same set of clock drivers so managing the dependencies was not a big concern. Since this ancient time, entropy did its job, controllers with different requirement and specific clock drivers have been added. Unfortunately, we did not do a great job at managing the dependencies between the controllers and the different clock drivers. Some drivers, such as clk-phase or vid-pll-div, are compiled even if they are useless on the target (meson8). As we are adding new controllers, we need to be able to pick a driver w/o pulling the whole thing. The patch aims to clean things up by: * providing a dedicated CONFIG_ for each clock drivers * allowing clock drivers to be compiled as a modules, if possible * stating explicitly which drivers are required by each controller. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201125841.26785-5-jbrunet@baylibre.com
* clk: meson: axg-audio does not require sysconJerome Brunet2019-02-021-1/+1
| | | | | | | | | The axg audio clock controller uses regmap mmio, not syscon. Fixes: 1cd50181750f ("clk: meson: axg: add the audio clock controller driver") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201125841.26785-4-jbrunet@baylibre.com
* clk: meson: axg: add the audio clock controller driverJerome Brunet2018-07-091-0/+9
| | | | | | | | | | | | | | The axg audio clock controller is the clock generation unit for the amlogic audio subsystem of A113 based SoCs. It may be clocked by 8 different plls provided by the primary clock controller and also by 10 slave bit clocks and 10 slave sample clocks which may be provided by external components, such as audio codecs, through the SoC pads. It contains several muxes, dividers and gates which are fed into the the different devices of the audio subsystem. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: add triple phase clock driverJerome Brunet2018-07-091-0/+5
| | | | | | | | | | | | | Add a driver to control the output of the sample clock generator found in the axg audio clock controller. The goal of this driver is to coherently control the phase provided to the different element using the sample clock generator. This simplify the usage of the sample clock generator a lot, without comprising the ability of the SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: clean-up meson clock configurationJerome Brunet2018-07-091-9/+5
| | | | | | | | | | Clean the dependencies in meson clock Kconfig. CLK_AMLOGIC should actually select CLK_REGMAP_MESON which it uses. Also, each platform should select CLK_AMLOGIC, so everything is properly turned on when the platform Kconfig enable each configuration flag Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson-axg: Add AO Clock and Reset controller driverQiufang Dai2018-05-151-0/+1
| | | | | | | | | Adds a Clock and Reset controller driver for the Always-On part of the Amlogic Meson-AXG SoC. Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: aoclk: refactor common code into dedicated fileYixun Lan2018-05-151-0/+7
| | | | | | | | | | We try to refactor the common code into one dedicated file, while preparing to add new Meson-AXG aoclk driver, this would help us to better share the code by all aoclk drivers. Suggested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: use hhi syscon if availableJerome Brunet2018-03-131-0/+2
| | | | | | | | | | | | | | | On gxbb and axg, try to get the hhi regmap from the parent DT node, which should be the HHI system controller once the necessary changes have been made in amlogic's DTs Until then, if getting regmap through the system controller fails, the clock controller will fall back to the old way, requesting memory region directly and then registering the regmap itself. This should allow a smooth transition to syscon Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: migrate gates to clk_regmapJerome Brunet2018-03-131-2/+2
| | | | | | | Move meson8b, gxbb and axg clocks using clk_gate to clk_regmap Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: add regmap to the clock controllersJerome Brunet2018-03-131-0/+2
| | | | | | | | | | | | | | This change registers a regmap in meson8b, gxbb and axg controllers. The clock are still accessing their registers directly through iomem. Once all clocks handled by these controllers have been move to regmap, the regmap register will be removed and replaced with a syscon request. This is needed because other drivers, such as the HDMI driver, need to access the HHI register region Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: switch gxbb ao_clk to clk_regmapJerome Brunet2018-03-131-0/+1
| | | | | | | | Drop the gxbb ao specific regmap based clock and use the meson clk_regmap based clock instead. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: add regmap clocksJerome Brunet2018-03-131-0/+4
| | | | | | | | | | | | | | | | | Meson clock controllers need to move the classical iomem registers to regmap. This is triggered because the HHI controllers found on the GXBB and GXL host more than just clocks. To properly handle this, we would like to migrate HHI to syscon. Also GXBB AO clock controller already use regmap, AXG AO and Audio clock controllers will as well. The purpose of this change is to provide a common structure to these meson controllers (and possibly others) for regmap based clocks. This change provides the basic gate, mux and divider, based on the helpers provided by the related generic clocks Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson-axg: add clock controller driversQiufang Dai2017-12-141-0/+8
| | | | | | | | | Add clock controller drivers for Amlogic Meson-AXG SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl2017-08-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The clock controller also includes some reset lines. This patch implements a reset controller to assert and de-assert these resets. The reset controller itself is registered early (through CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot process (to start the secondary CPU cores). According to the public S805 datasheet there are two more reset bits in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by this patch (as these seem to be unused in Amlogic's vendor Linux kernel sources and their u-boot tree): - bit 15: GEN_DIV_SOFT_RESET - bit 14: SOFT_RESET All information was taken from the public S805 Datasheet and Amlogic's vendor GPL kernel sources. This patch is based on an earlier version submitted by Carlo Caione. Suggested-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into ↵Stephen Boyd2017-06-171-3/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next Pull Amlogic clk driver updates from Jerome Brunet: * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH) * Add new compatible to the meson8 clock controller for meson8b * Add missing parents to gxbb clk81 * tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson: clk: meson: gxbb: add all clk81 parents clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 clk: meson8b: export the ethernet gate clock clk: meson8b: export the USB clocks clk: meson8b: export the gate clock for the HW random number generator clk: meson8b: export the SDIO clock clk: meson8b: export the SAR ADC clocks
| * clk: meson: meson8b: add compatibles for Meson8 and Meson8m2Martin Blumenstingl2017-06-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock controller on Meson8, Meson8b and Meson8m2 is very similar based on the code from the Amlogic GPL kernel sources. Add separate compatibles for each SoC to make sure that we can easily implement all the small differences for each SoC later on. In general the Meson8 and Meson8m2 seem to be almost identical as they even share the same mach-meson8 directory in Amlogic's GPL kernel sources. The main clocks on Meson8, Meson8b and Meson8m2 are very similar, because they are all using the same PLL values, 90% of the clock gates are the same (the actual diffstat of the mach-meson8/clock.c and mach-meson8b/clock.c files is around 30 to 40 lines, when excluding all commented out code). The difference between the Meson8 and Meson8b clock gates seem to be: - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, CSI_DIG_CLKIN gates which don't seem to be available on Meson8b - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead of "PERIPHS_TOP" (on Meson8b) - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL kernel sources) None of these gates is added for now, since it's unclear whether these definitions are actually correct (the VCLK2_ENCT gate for example is defined, but only used in some commented block). The main difference between all three SoCs seem to be the video (VPU) clocks. Apart from different supported clock rates (according to vpu.c in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the most notable difference is that Meson8m2 has a GP_PLL clock and a mux (probably the same as on the Meson GX SoCs) to support glitch-free (clock rate) switching. None of these VPU clocks are not supported by our mainline meson8b clock driver yet though. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* | clk: meson: gxbb: fix build error without RESET_CONTROLLERTobias Regnery2017-05-161-0/+1
|/ | | | | | | | | | | | | | | | With CONFIG_RESET_CONTROLLER=n we see the following link error in the meson gxbb clk driver: drivers/built-in.o: In function 'gxbb_aoclkc_probe': drivers/clk/meson/gxbb-aoclk.c:161: undefined reference to 'devm_reset_controller_register' Fix this by selecting the reset controller subsystem. Fixes: f8c11f79912d ("clk: meson: Add GXBB AO Clock and Reset controller driver") Signed-off-by: Tobias Regnery <tobias.regnery@gmail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> [narmstrong: Added fixes-by tag] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: gxbb: add AmLogic GXBB clk controller driverMichael Turquette2016-06-231-0/+7
| | | | | | | | | | The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* clk: meson: only build selected platformsMichael Turquette2016-06-231-0/+12
Break the AmLogic clock code up so that only the necessary parts are compiled and linked. The core code is selected by both arm and arm64 builds with COMMON_CLK_AMLOGIC. The individual drivers have their own config options as well. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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