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path: root/drivers/clk/meson/gxbb.c (follow)
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*-. Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd2023-08-301-424/+424
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| | * clk: meson: eeclk: move bindings include to main driverNeil Armstrong2023-08-081-0/+2
| | * clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong2023-08-081-424/+422
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* / clk: Explicitly include correct DT includesRob Herring2023-07-191-1/+1
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* clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBBMartin Blumenstingl2021-11-301-3/+41
* clk: meson: enable building as modulesKevin Hilman2020-11-231-1/+4
* clk: meson: gxbb: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl2020-04-161-18/+22
* clk: meson: gxbb: set audio output clock hierarchyJerome Brunet2020-02-131-8/+10
* clk: meson: gxbb: add the gxl internal dac gateJerome Brunet2020-02-131-0/+3
* clk: meson: gxbb: let sar_adc_clk_div set the parent clock rateMartin Blumenstingl2019-10-011-0/+1
* clk: meson: clk-regmap: migrate to new parent description methodAlexandre Mergnat2019-07-291-0/+3
* clk: meson: gxbb: migrate to the new parent description methodAlexandre Mergnat2019-07-291-203/+451
* clk: meson: gxbb: no spread spectrum on mpll0Jerome Brunet2019-05-201-5/+0
* clk: meson-gxbb: round the vdec dividers to closestMaxime Jourdan2019-03-191-0/+2
* clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet2019-02-041-75/+197
* clk: meson: rework and clean drivers dependenciesJerome Brunet2019-02-021-1/+4
* clk: meson: gxbb: claim clock controller input clock from DTJerome Brunet2019-01-181-13/+24
* Merge branch 'clk-fixes' into clk-nextStephen Boyd2018-12-141-0/+12
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| * clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICALChristian Hewitt2018-11-081-0/+12
* | Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into cl...Stephen Boyd2018-12-131-1/+7
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| * | clk: meson: Fix GXL HDMI PLL fractional bits widthNeil Armstrong2018-11-271-1/+7
* | | clk: meson: Mark some things staticStephen Boyd2018-12-031-4/+4
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* | clk: meson-gxbb: Add video clocksNeil Armstrong2018-11-231-0/+722
* | clk: meson-gxbb: Fix HDMI PLL for GXL SoCsNeil Armstrong2018-11-231-2/+49
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* clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet2018-09-261-60/+60
* clk: meson: clk-pll: remove od parametersJerome Brunet2018-09-261-256/+228
* clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet2018-09-261-4/+8
* clk: meson: clk-pll: add enable bitJerome Brunet2018-09-261-2/+30
* clk: meson: add gen_clkJerome Brunet2018-07-091-0/+66
* clk: meson: stop rate propagation for audio clocksJerome Brunet2018-07-091-9/+7
* clk: meson: remove obsolete register accessJerome Brunet2018-07-091-34/+2
* clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICALNeil Armstrong2018-06-191-0/+1
* clk: meson: use SPDX license identifiers consistentlyJerome Brunet2018-05-181-14/+1
* clk: meson: gxbb: add the video decoder clocksMaxime Jourdan2018-05-151-0/+114
* clk: meson: Drop unused local variable and add staticStephen Boyd2018-03-141-2/+2
* clk: meson: clean-up clk81 clocksJerome Brunet2018-03-131-4/+2
* clk: meson: add fdiv clock gatesJerome Brunet2018-03-131-10/+90
* clk: meson: add mpll pre-dividerJerome Brunet2018-03-131-3/+20
* clk: meson: add gp0 frac parameter for axg and gxlJerome Brunet2018-03-131-1/+6
* clk: meson: remove special gp0 lock loopJerome Brunet2018-03-131-1/+0
* clk: meson: poke pll CNTL lastJerome Brunet2018-03-131-2/+2
* clk: meson: use hhi syscon if availableJerome Brunet2018-03-131-11/+28
* clk: meson: split divider and gate part of mpllJerome Brunet2018-03-131-21/+57
* clk: meson: migrate plls clocks to clk_regmapJerome Brunet2018-03-131-185/+239
* clk: meson: migrate the audio divider clock to clk_regmapJerome Brunet2018-03-131-21/+9
* clk: meson: migrate mplls clocks to clk_regmapJerome Brunet2018-03-131-84/+77
* clk: meson: migrate muxes to clk_regmapJerome Brunet2018-03-131-160/+150
* clk: meson: migrate dividers to clk_regmapJerome Brunet2018-03-131-109/+108
* clk: meson: migrate gates to clk_regmapJerome Brunet2018-03-131-129/+137
* clk: meson: add regmap to the clock controllersJerome Brunet2018-03-131-10/+23
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