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path: root/drivers/clk/meson/meson8b.c (follow)
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-06-091-15/+62
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| * clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICALMartin Blumenstingl2018-05-211-0/+7
| * clk: meson: use SPDX license identifiers consistentlyJerome Brunet2018-05-181-15/+1
| * clk: meson: meson8b: add support for the NAND clocksMartin Blumenstingl2018-05-151-0/+54
* | clk: meson: meson8b: fix meson8b_cpu_clk parent clock nameMartin Blumenstingl2018-04-251-1/+2
* | clk: meson: meson8b: fix meson8b_fclk_div3_div clock nameMartin Blumenstingl2018-04-251-1/+1
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* clk: meson: Drop unused local variable and add staticStephen Boyd2018-03-141-7/+6
* clk: meson: clean-up clk81 clocksJerome Brunet2018-03-131-4/+2
* clk: meson: add fdiv clock gatesJerome Brunet2018-03-131-10/+85
* clk: meson: add mpll pre-dividerJerome Brunet2018-03-131-3/+19
* clk: meson: add fractional part of meson8b fixed_pllJerome Brunet2018-03-131-0/+5
* clk: meson: rework meson8b cpu clockJerome Brunet2018-03-131-60/+113
* clk: meson: split divider and gate part of mpllJerome Brunet2018-03-131-21/+54
* clk: meson: migrate plls clocks to clk_regmapJerome Brunet2018-03-131-62/+87
* clk: meson: migrate mplls clocks to clk_regmapJerome Brunet2018-03-131-78/+77
* clk: meson: migrate muxes to clk_regmapJerome Brunet2018-03-131-18/+9
* clk: meson: migrate dividers to clk_regmapJerome Brunet2018-03-131-15/+8
* clk: meson: migrate gates to clk_regmapJerome Brunet2018-03-131-19/+20
* clk: meson: add regmap to the clock controllersJerome Brunet2018-03-131-1/+13
* clk: meson: remove obsolete commentsJerome Brunet2018-03-131-1/+0
* clk: meson: only one loop index is necessary in probeJerome Brunet2018-03-131-4/+4
* clk: meson: use devm_of_clk_add_hw_providerJerome Brunet2018-03-131-2/+2
* clk: meson: make the spinlock naming more specificYixun Lan2017-12-141-12/+12
* Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into cl...Stephen Boyd2017-08-241-12/+148
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| * clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl2017-08-041-12/+147
| * clk: meson: meson8b: fix protection against undefined clksJerome Brunet2017-08-041-0/+1
* | clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet2017-08-011-0/+5
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* clk: meson: meson8b: add compatibles for Meson8 and Meson8m2Martin Blumenstingl2017-06-121-1/+4
* clk: meson: meson8b: mark clk81 as criticalMartin Blumenstingl2017-05-291-1/+1
* clk: meson8b: add the mplls clocks 0, 1 and 2Jerome Brunet2017-03-271-0/+103
* clk: meson8b: put dividers and muxes in tablesJerome Brunet2017-03-271-4/+18
* clk: meson: add missing const qualifiers on gate arraysJerome Brunet2017-03-271-1/+1
* clk: meson8b: fix clk81 register addressJerome Brunet2017-01-271-1/+0
* clk: meson: fix CLKID_GCLK_VENCI_INT typoArnd Bergmann2016-09-141-1/+1
* meson: clk: Use builtin_platform_driver to simplify the codeWei Yongjun2016-09-141-5/+1
* meson: clk: Add support for clock gatesAlexander Müller2016-09-021-0/+249
* clk: meson: Copy meson8b CLKID defines to private header fileAlexander Müller2016-09-021-1/+0
* meson: clk: Rename register names according to Amlogic datasheetAlexander Müller2016-09-021-13/+13
* meson: clk: Move register definitions to meson8b.hAlexander Müller2016-09-021-16/+1
* clk: meson: Rename meson8b-clkc.c to reflect gxbb naming conventionAlexander Müller2016-09-021-0/+447
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