| Commit message (Expand) | Author | Age | Files | Lines |
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| * | clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers | Martin Blumenstingl | 2020-05-02 | 2 | -0/+13 |
| * | clk: meson: meson8b: Make the CCF use the glitch-free VPU mux | Martin Blumenstingl | 2020-04-29 | 1 | -3/+11 |
| * | clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits | Martin Blumenstingl | 2020-04-29 | 1 | -5/+5 |
| * | clk: meson: meson8b: Fix the polarity of the RESET_N lines | Martin Blumenstingl | 2020-04-29 | 1 | -23/+56 |
| * | clk: meson: meson8b: Fix the first parent of vid_pll_in_sel | Martin Blumenstingl | 2020-04-29 | 1 | -1/+1 |
| * | clk: meson: g12a: Prepare the GPU clock tree to change at runtime | Martin Blumenstingl | 2020-04-16 | 1 | -8/+22 |
| * | clk: meson: gxbb: Prepare the GPU clock tree to change at runtime | Martin Blumenstingl | 2020-04-16 | 1 | -18/+22 |
| * | clk: meson: meson8b: make the hdmi_sys clock tree mutable | Martin Blumenstingl | 2020-04-14 | 1 | -3/+3 |
| * | clk: meson8b: export the HDMI system clock | Martin Blumenstingl | 2020-04-14 | 1 | -1/+0 |
| * | clk: meson: meson8b: set audio output clock hierarchy | Martin Blumenstingl | 2020-02-21 | 1 | -8/+13 |
| * | clk: meson: g12a: add support for the SPICC SCLK Source clocks | Neil Armstrong | 2020-02-19 | 2 | -1/+134 |
| * | clk: meson: gxbb: set audio output clock hierarchy | Jerome Brunet | 2020-02-13 | 1 | -8/+10 |
| * | clk: meson: gxbb: add the gxl internal dac gate | Jerome Brunet | 2020-02-13 | 2 | -1/+4 |
| *-. | Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlo... | Stephen Boyd | 2020-01-31 | 5 | -56/+229 |
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| | | * | clk: meson: meson8b: make the CCF use the glitch-free mali mux | Martin Blumenstingl | 2020-01-07 | 1 | -4/+7 |
| | | * | Merge branch 'v5.5/fixes' into v5.6/drivers | Jerome Brunet | 2019-12-16 | 2 | -0/+10 |
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| | | | * | clk: meson: pll: Fix by 0 division in __pll_params_to_rate() | Remi Pommarel | 2019-12-16 | 1 | -0/+9 |
| | | | * | clk: meson: g12a: fix missing uart2 in regmap table | Jerome Brunet | 2019-12-16 | 1 | -0/+1 |
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| | | * | clk: meson: meson8b: use of_clk_hw_register to register the clocks | Martin Blumenstingl | 2019-12-11 | 1 | -1/+1 |
| | | * | clk: meson: meson8b: don't register the XTAL clock when provided via OF | Martin Blumenstingl | 2019-12-11 | 1 | -3/+9 |
| | | * | clk: meson: meson8b: change references to the XTAL clock to use [fw_]name | Martin Blumenstingl | 2019-12-11 | 1 | -34/+44 |
| | | * | clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier | Martin Blumenstingl | 2019-12-11 | 1 | -13/+8 |
| | | * | clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller | Martin Blumenstingl | 2019-12-11 | 2 | -1/+150 |
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| * / | clk: let init callback return an error code | Jerome Brunet | 2019-12-24 | 4 | -4/+12 |
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| * | clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code | YueHaibing | 2019-10-14 | 1 | -3/+1 |
| * | clk: meson: axg_audio: add sm1 support | Jerome Brunet | 2019-10-08 | 2 | -30/+574 |
| * | clk: meson: axg-audio: provide clk top signal name | Jerome Brunet | 2019-10-08 | 2 | -4/+17 |
| * | clk: meson: axg-audio: prepare sm1 addition | Jerome Brunet | 2019-10-08 | 1 | -685/+782 |
| * | clk: meson: axg-audio: fix regmap last register | Jerome Brunet | 2019-10-08 | 1 | -1/+1 |
| * | clk: meson: axg-audio: remove useless defines | Jerome Brunet | 2019-10-08 | 1 | -4/+0 |
| * | clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes | Neil Armstrong | 2019-10-01 | 1 | -0/+9 |
| * | clk: meson: g12a: fix cpu clock rate setting | Neil Armstrong | 2019-10-01 | 1 | -2/+2 |
| * | clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate | Martin Blumenstingl | 2019-10-01 | 1 | -0/+1 |
| *-. | Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' i... | Stephen Boyd | 2019-09-20 | 1 | -2/+5 |
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| | * | | clk: meson: axg-audio: Don't reference clk_init_data after registration | Stephen Boyd | 2019-08-16 | 1 | -2/+5 |
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| * | | clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks | Neil Armstrong | 2019-08-26 | 2 | -1/+61 |
| * | | clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock | Neil Armstrong | 2019-08-26 | 2 | -1/+198 |
| * | | clk: meson: g12a: add support for SM1 GP1 PLL | Neil Armstrong | 2019-08-26 | 2 | -1/+310 |
| * | | clk: meson: axg-audio: add g12a reset support | Jerome Brunet | 2019-08-20 | 2 | -2/+106 |
| * | | Merge branch 'v5.4/dt' into v5.4/drivers | Jerome Brunet | 2019-08-09 | 1 | -1/+0 |
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| | * | | clk: meson: g12a: expose CPUB clock ID for G12B | Neil Armstrong | 2019-08-09 | 1 | -1/+0 |
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| * | | clk: meson: g12a: add notifiers to handle cpu clock change | Neil Armstrong | 2019-08-09 | 1 | -54/+481 |
| * | | clk: meson: add g12a cpu dynamic divider driver | Neil Armstrong | 2019-08-09 | 4 | -0/+99 |
| * | | clk: meson: remove clk input helper | Alexandre Mergnat | 2019-07-29 | 4 | -72/+0 |
| * | | clk: meson: remove ee input bypass clocks | Alexandre Mergnat | 2019-07-29 | 3 | -13/+0 |
| * | | clk: meson: clk-regmap: migrate to new parent description method | Alexandre Mergnat | 2019-07-29 | 5 | -6/+21 |
| * | | clk: meson: meson8b: migrate to the new parent description method | Alexandre Mergnat | 2019-07-29 | 1 | -211/+496 |
| * | | clk: meson: axg: migrate to the new parent description method | Alexandre Mergnat | 2019-07-29 | 1 | -60/+144 |
| * | | clk: meson: gxbb: migrate to the new parent description method | Alexandre Mergnat | 2019-07-29 | 1 | -203/+451 |
| * | | clk: meson: g12a: migrate to the new parent description method | Alexandre Mergnat | 2019-07-29 | 1 | -394/+693 |
