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* clk: meson: add gen_clkJerome Brunet2018-07-094-3/+135
* clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definitionJerome Brunet2018-07-091-1/+0
* clk: meson-axg: add clocks required by pcie driverYixun Lan2018-07-092-1/+150
* clk: meson: remove unused clk-audio-divider driverJerome Brunet2018-07-093-119/+1
* clk: meson: stop rate propagation for audio clocksJerome Brunet2018-07-091-9/+7
* clk: meson: axg: add the audio clock controller driverJerome Brunet2018-07-094-0/+982
* clk: meson: add axg audio sclk divider driverJerome Brunet2018-07-093-1/+252
* clk: meson: add triple phase clock driverJerome Brunet2018-07-094-0/+94
* clk: meson: add clk-phase clock driverJerome Brunet2018-07-093-0/+72
* clk: meson: clean-up meson clock configurationJerome Brunet2018-07-091-9/+5
* clk: meson: remove obsolete register accessJerome Brunet2018-07-092-69/+4
* clk: meson: audio-divider is one basedJerome Brunet2018-06-211-1/+1
* clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICALNeil Armstrong2018-06-191-0/+1
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-06-0920-309/+586
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| * clk: meson: axg: let mpll clocks round closestJerome Brunet2018-05-211-0/+4
| * clk: meson: mpll: add round closest supportJerome Brunet2018-05-212-5/+22
| * clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICALMartin Blumenstingl2018-05-211-0/+7
| * clk: meson: use SPDX license identifiers consistentlyJerome Brunet2018-05-1813-238/+20
| * clk: meson: drop CLK_SET_RATE_PARENT flagYixun Lan2018-05-151-1/+1
| * clk: meson-axg: Add AO Clock and Reset controller driverQiufang Dai2018-05-154-1/+195
| * clk: meson: aoclk: refactor common code into dedicated fileYixun Lan2018-05-156-62/+160
| * clk: meson: migrate to devm_of_clk_add_hw_provider APIYixun Lan2018-05-151-1/+1
| * clk: meson: gxbb: add the video decoder clocksMaxime Jourdan2018-05-152-1/+119
| * clk: meson: meson8b: add support for the NAND clocksMartin Blumenstingl2018-05-152-1/+58
* | Merge tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson i...Stephen Boyd2018-05-012-4/+3
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| * | clk: meson: meson8b: fix meson8b_cpu_clk parent clock nameMartin Blumenstingl2018-04-251-1/+2
| * | clk: meson: meson8b: fix meson8b_fclk_div3_div clock nameMartin Blumenstingl2018-04-251-1/+1
| * | clk: meson: drop meson_aoclk_gate_regmap_opsYixun Lan2018-04-251-2/+0
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* / clk: meson: honor CLK_MUX_ROUND_CLOSEST in clk_regmapJerome Brunet2018-04-161-1/+10
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* clk: meson: Drop unused local variable and add staticStephen Boyd2018-03-143-11/+10
* clk: meson: clean-up clk81 clocksJerome Brunet2018-03-132-8/+4
* clk: meson: add fdiv clock gatesJerome Brunet2018-03-136-33/+278
* clk: meson: add mpll pre-dividerJerome Brunet2018-03-136-13/+65
* clk: meson: axg: add hifi pll clockJerome Brunet2018-03-132-1/+56
* clk: meson: add ROUND_CLOSEST to the pll driverJerome Brunet2018-03-132-4/+15
* clk: meson: add gp0 frac parameter for axg and gxlJerome Brunet2018-03-132-2/+12
* clk: meson: improve pll driver results with fracJerome Brunet2018-03-132-59/+91
* clk: meson: remove special gp0 lock loopJerome Brunet2018-03-134-15/+1
* clk: meson: poke pll CNTL lastJerome Brunet2018-03-132-3/+3
* clk: meson: add fractional part of meson8b fixed_pllJerome Brunet2018-03-131-0/+5
* clk: meson: use hhi syscon if availableJerome Brunet2018-03-133-24/+60
* clk: meson: remove obsolete cpu_clkJerome Brunet2018-03-133-190/+1
* clk: meson: rework meson8b cpu clockJerome Brunet2018-03-132-61/+119
* clk: meson: split divider and gate part of mpllJerome Brunet2018-03-138-118/+197
* clk: meson: migrate plls clocks to clk_regmapJerome Brunet2018-03-135-530/+535
* clk: meson: migrate the audio divider clock to clk_regmapJerome Brunet2018-03-133-68/+30
* clk: meson: migrate mplls clocks to clk_regmapJerome Brunet2018-03-135-354/+313
* clk: meson: add regmap helpers for parmJerome Brunet2018-03-131-0/+16
* clk: meson: migrate muxes to clk_regmapJerome Brunet2018-03-133-213/+184
* clk: meson: migrate dividers to clk_regmapJerome Brunet2018-03-133-159/+142
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 16:29:44 +0100