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* | clk: meson: clk-regmap: add read-only gate opsMartin Blumenstingl2018-11-232-0/+6
* | clk: meson: meson8b: allow changing the CPU clock treeMartin Blumenstingl2018-11-231-6/+6
* | clk: meson: meson8b: run from the XTAL when changing the CPU frequencyMartin Blumenstingl2018-11-231-0/+63
* | clk: meson: meson8b: add support for more M/N values in sys_pllMartin Blumenstingl2018-11-231-0/+5
* | clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICALMartin Blumenstingl2018-11-231-1/+2
* | clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_selMartin Blumenstingl2018-11-231-2/+9
* | clk: meson: clk-pll: check if the clock is already enabledMartin Blumenstingl2018-11-231-0/+19
* | clk: meson: meson8b: fix the width of the cpu_scale_div clockMartin Blumenstingl2018-11-231-1/+1
* | clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_tableMartin Blumenstingl2018-11-231-7/+8
* | clk: meson: meson8b: use the HHI syscon if availableMartin Blumenstingl2018-11-231-9/+15
* | clk: meson-gxbb: Add video clocksNeil Armstrong2018-11-231-0/+722
* | dt-bindings: clk: meson-gxbb: Add Video clock bindingsNeil Armstrong2018-11-231-2/+24
* | clk: meson-gxbb: Fix HDMI PLL for GXL SoCsNeil Armstrong2018-11-231-2/+49
* | clk: meson: Add vid_pll divider driverNeil Armstrong2018-11-233-1/+98
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* clk: meson: meson8b: use the regmap in the internal reset controllerMartin Blumenstingl2018-09-261-7/+6
* clk: meson: meson8b: register the clock controller earlyMartin Blumenstingl2018-09-261-60/+34
* clk: meson-axg: pcie: drop the mpll3 clock parentYixun Lan2018-09-261-2/+4
* clk: meson: axg: round audio system master clocks downJerome Brunet2018-09-261-11/+23
* clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet2018-09-265-142/+162
* clk: meson: clk-pll: remove od parametersJerome Brunet2018-09-268-498/+493
* clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet2018-09-263-8/+8
* clk: meson: clk-pll: add enable bitJerome Brunet2018-09-265-10/+113
* clk: meson: add gen_clkJerome Brunet2018-07-094-3/+135
* clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definitionJerome Brunet2018-07-091-1/+0
* clk: meson-axg: add clocks required by pcie driverYixun Lan2018-07-092-1/+150
* clk: meson: remove unused clk-audio-divider driverJerome Brunet2018-07-093-119/+1
* clk: meson: stop rate propagation for audio clocksJerome Brunet2018-07-091-9/+7
* clk: meson: axg: add the audio clock controller driverJerome Brunet2018-07-094-0/+982
* clk: meson: add axg audio sclk divider driverJerome Brunet2018-07-093-1/+252
* clk: meson: add triple phase clock driverJerome Brunet2018-07-094-0/+94
* clk: meson: add clk-phase clock driverJerome Brunet2018-07-093-0/+72
* clk: meson: clean-up meson clock configurationJerome Brunet2018-07-091-9/+5
* clk: meson: remove obsolete register accessJerome Brunet2018-07-092-69/+4
* clk: meson: audio-divider is one basedJerome Brunet2018-06-211-1/+1
* clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICALNeil Armstrong2018-06-191-0/+1
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2018-06-0920-309/+586
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| * clk: meson: axg: let mpll clocks round closestJerome Brunet2018-05-211-0/+4
| * clk: meson: mpll: add round closest supportJerome Brunet2018-05-212-5/+22
| * clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICALMartin Blumenstingl2018-05-211-0/+7
| * clk: meson: use SPDX license identifiers consistentlyJerome Brunet2018-05-1813-238/+20
| * clk: meson: drop CLK_SET_RATE_PARENT flagYixun Lan2018-05-151-1/+1
| * clk: meson-axg: Add AO Clock and Reset controller driverQiufang Dai2018-05-154-1/+195
| * clk: meson: aoclk: refactor common code into dedicated fileYixun Lan2018-05-156-62/+160
| * clk: meson: migrate to devm_of_clk_add_hw_provider APIYixun Lan2018-05-151-1/+1
| * clk: meson: gxbb: add the video decoder clocksMaxime Jourdan2018-05-152-1/+119
| * clk: meson: meson8b: add support for the NAND clocksMartin Blumenstingl2018-05-152-1/+58
* | Merge tag 'meson-clk-fixes-4.17-1' of https://github.com/BayLibre/clk-meson i...Stephen Boyd2018-05-012-4/+3
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| * | clk: meson: meson8b: fix meson8b_cpu_clk parent clock nameMartin Blumenstingl2018-04-251-1/+2
| * | clk: meson: meson8b: fix meson8b_fclk_div3_div clock nameMartin Blumenstingl2018-04-251-1/+1
| * | clk: meson: drop meson_aoclk_gate_regmap_opsYixun Lan2018-04-251-2/+0
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