| Commit message (Expand) | Author | Age | Files | Lines |
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| *-. | Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' ... | Stephen Boyd | 2022-12-12 | 1 | -8/+12 |
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| | | * | clk: meson: pll: add pcie lock retry workaround | Heiner Kallweit | 2022-11-08 | 1 | -4/+8 |
| | | * | clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock() | Heiner Kallweit | 2022-11-08 | 1 | -4/+4 |
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| * / | clk: Remove a useless include | Christophe JAILLET | 2022-11-23 | 1 | -1/+0 |
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| * | clk: meson: Hold reference returned by of_get_parent() | Liang He | 2022-08-19 | 3 | -3/+12 |
| * | clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled() | Uwe Kleine-König | 2022-06-16 | 1 | -32/+4 |
| * | clk: cleanup comments | Tom Rix | 2022-03-12 | 1 | -1/+1 |
| * | clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB | Martin Blumenstingl | 2021-11-30 | 1 | -3/+41 |
| * | clk: meson: meson8b: Make the video clock trees mutable | Martin Blumenstingl | 2021-09-23 | 1 | -38/+38 |
| * | clk: meson: meson8b: Initialize the HDMI PLL registers | Martin Blumenstingl | 2021-09-23 | 2 | -5/+48 |
| * | clk: meson: meson8b: Add the HDMI PLL M/N parameters | Martin Blumenstingl | 2021-09-23 | 1 | -0/+22 |
| * | clk: meson: meson8b: Add the vid_pll_lvds_en gate clock | Martin Blumenstingl | 2021-09-23 | 2 | -2/+24 |
| * | clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel | Martin Blumenstingl | 2021-09-23 | 1 | -2/+2 |
| * | clk: meson: meson8b: Export the video clocks | Martin Blumenstingl | 2021-09-23 | 1 | -11/+1 |
| * | clk: meson: regmap: switch to determine_rate for the dividers | Martin Blumenstingl | 2021-06-30 | 1 | -10/+9 |
| * | clk: meson: g12a: Add missing NNA source clocks for g12b | Nick Xie | 2021-06-09 | 1 | -0/+6 |
| * | clk: meson: axg-audio: improve deferral handling | Jerome Brunet | 2021-05-24 | 1 | -3/+2 |
| * | clk: meson: g12a: fix gp0 and hifi ranges | Jerome Brunet | 2021-05-20 | 1 | -1/+1 |
| * | clk: meson: pll: switch to determine_rate for the PLL ops | Martin Blumenstingl | 2021-05-19 | 1 | -11/+15 |
| * | clk: meson: axg: Remove MIPI enable clock gate | Remi Pommarel | 2021-02-09 | 2 | -4/+0 |
| * | clk: meson: meson8b: remove compatibility code for old .dtbs | Martin Blumenstingl | 2021-01-04 | 1 | -40/+5 |
| * | clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate() | Martin Blumenstingl | 2021-01-04 | 1 | -2/+3 |
| * | clk: meson: clk-pll: make "ret" a signed integer | Martin Blumenstingl | 2021-01-04 | 1 | -1/+2 |
| * | clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL | Martin Blumenstingl | 2021-01-04 | 1 | -1/+1 |
| * | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 2020-12-21 | 11 | -61/+1004 |
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| | * | clk: meson: g12a: add MIPI DSI Host Pixel Clock | Neil Armstrong | 2020-11-26 | 2 | -1/+76 |
| | * | clk: meson: enable building as modules | Kevin Hilman | 2020-11-23 | 9 | -9/+34 |
| | * | clk: meson: Kconfig: fix dependency for G12A | Kevin Hilman | 2020-11-23 | 1 | -0/+1 |
| | * | clk: meson: axg: add MIPI DSI Host clock | Neil Armstrong | 2020-11-23 | 2 | -1/+69 |
| | * | clk: meson: axg: add Video Clocks | Neil Armstrong | 2020-11-23 | 2 | -1/+773 |
| | * | clk: meson: g12: use devm variant to register notifiers | Jerome Brunet | 2020-11-14 | 1 | -14/+20 |
| | * | clk: meson: g12: drop use of __clk_lookup() | Jerome Brunet | 2020-11-14 | 1 | -36/+32 |
| * | | clk: define to_clk_regmap() as inline function | Arnd Bergmann | 2020-10-29 | 1 | -1/+4 |
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| *-. | Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', ... | Stephen Boyd | 2020-10-20 | 1 | -1/+1 |
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| | * | | clk: meson: use semicolons rather than commas to separate statements | Julia Lawall | 2020-10-14 | 1 | -1/+1 |
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| * | | clk: meson: make shipped controller configurable | Jerome Brunet | 2020-09-10 | 1 | -9/+17 |
| * | | clk: meson: g12a: mark fclk_div2 as critical | Stefan Agner | 2020-08-29 | 1 | -0/+11 |
| * | | clk: meson: axg-audio: fix g12a tdmout sclk inverter | Jerome Brunet | 2020-08-17 | 1 | -25/+60 |
| * | | clk: meson: axg-audio: separate axg and g12a regmap tables | Jerome Brunet | 2020-08-17 | 1 | -8/+127 |
| * | | clk: meson: add sclk-ws driver | Jerome Brunet | 2020-08-17 | 2 | -0/+62 |
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| * | Merge branch 'clk-amlogic' into clk-next | Stephen Boyd | 2020-07-21 | 4 | -19/+178 |
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| | * | clk: meson: meson8b: add the vclk2_en gate clock | Martin Blumenstingl | 2020-07-09 | 2 | -6/+27 |
| | * | clk: meson: meson8b: add the vclk_en gate clock | Martin Blumenstingl | 2020-07-09 | 2 | -6/+27 |
| | * | clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 | Martin Blumenstingl | 2020-06-24 | 1 | -7/+0 |
| | * | clk: meson: g12a: Add support for NNA CLK source clocks | Dmitry Shmidt | 2020-06-19 | 2 | -1/+125 |
| * | | Replace HTTP links with HTTPS ones: Common CLK framework | Alexander A. Klimov | 2020-07-11 | 1 | -1/+1 |
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| * | clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers | Martin Blumenstingl | 2020-05-02 | 2 | -0/+13 |
| * | clk: meson: meson8b: Make the CCF use the glitch-free VPU mux | Martin Blumenstingl | 2020-04-29 | 1 | -3/+11 |
| * | clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits | Martin Blumenstingl | 2020-04-29 | 1 | -5/+5 |
| * | clk: meson: meson8b: Fix the polarity of the RESET_N lines | Martin Blumenstingl | 2020-04-29 | 1 | -23/+56 |
