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Author
Files
Lines
2016-04-16
clk: clps711x: Remove CLK_IS_ROOT
Stephen Boyd
1
-11
/
+8
2016-04-16
clk: zte: Remove CLK_IS_ROOT
Stephen Boyd
1
-2
/
+1
2016-04-16
clk: sunxi: Remove CLK_IS_ROOT
Stephen Boyd
1
-2
/
+1
2016-04-16
clk: sirf: Remove CLK_IS_ROOT
Stephen Boyd
2
-8
/
+6
2016-04-16
clk: mmp: Remove CLK_IS_ROOT
Stephen Boyd
7
-38
/
+30
2016-04-16
clk: meson: Remove CLK_IS_ROOT
Stephen Boyd
1
-3
/
+3
2016-04-16
clk: add artpec-6 clock controller
Lars Persson
4
-1
/
+245
2016-04-16
clk: add device tree binding for Artpec-6 clock controller
Lars Persson
2
-0
/
+79
2016-04-16
clk: ti: dflt: remove redundant unlikely
Suman Anna
1
-1
/
+1
2016-04-16
clk: Add clk_composite_set_rate_and_parent
Finley Xiao
1
-0
/
+33
2016-04-15
clk: samsung: exynos542x: Add the clock id for ACLK
Chanwoo Choi
1
-30
/
+47
2016-04-15
dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC
Chanwoo Choi
1
-1
/
+23
2016-04-12
clk: imx: vf610: fix whitespace in vf610-clock.h
Shawn Guo
1
-1
/
+1
2016-04-12
clk: imx: vf610: add TCON ipg clock
Stefan Agner
2
-1
/
+6
2016-04-12
clk: imx: vf610: fix DCU clock tree
Stefan Agner
1
-2
/
+2
2016-04-09
clk: Provide OF helper to mark clocks as CRITICAL
Lee Jones
2
-1
/
+42
2016-04-09
clk: WARN_ON about to disable a critical clock
Lee Jones
1
-0
/
+6
2016-04-09
clk: Allow clocks to be marked as CRITICAL
Lee Jones
2
-0
/
+6
2016-04-07
clk: renesas: mstp: Clarify cpg_mstp_{at,de}tach_dev() domain parameter
Geert Uytterhoeven
2
-4
/
+4
2016-04-07
clk: renesas: cpg-mssr: Drop check for CONFIG_PM_GENERIC_DOMAINS_OF
Geert Uytterhoeven
1
-11
/
+0
2016-04-07
clk: renesas: mstp: Drop check for CONFIG_PM_GENERIC_DOMAINS_OF
Geert Uytterhoeven
2
-7
/
+0
2016-04-06
clk: imx: add ckil clock for i.MX7
Gary Bisson
2
-2
/
+4
2016-04-06
clk: renesas: r8a7795: add RWDT clock
Wolfram Sang
1
-0
/
+1
2016-04-06
clk: renesas: r8a7795: add R clk
Wolfram Sang
1
-0
/
+16
2016-04-06
clk: renesas: r8a7795: add OSC and RINT clocks
Wolfram Sang
1
-0
/
+5
2016-04-06
clk: renesas: cpg-mssr: add generic support for read-only DIV6 clocks
Wolfram Sang
2
-6
/
+15