linux - linux

	Commit message (Collapse)	Author	Age	Files	Lines
*	cpufreq: kirkwood: Add a cpufreq driver for Marvell Kirkwood SoCs	Andrew Lunn	2013-02-09	1	-0/+1
\| \| \| \| \| \| \| \| \| \| \|	The Marvell Kirkwood SoCs have simple cpufreq support in hardware. The CPU can either use the a high speed cpu clock, or the slower DDR clock. Add a driver to swap between these two clock sources. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
*	clk: mvebu/clk-cpu.c: fix memory leakage	Cong Ding	2013-01-23	1	-3/+6
\| \| \| \| \| \| \| \| \| \|	the variable cpuclk and clk_name should be properly freed when error happens. Signed-off-by: Cong Ding <dinggnu@gmail.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
*	clk: mvebu: Remove inappropriate __init tagging	Joshua Coombs	2013-01-06	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \|	If the Orion WDT driver is built as a module, an opps occurs during clk lookup when calling mvebu_clk_gating_get_src(). Remove the inappropriate __init tag so the function is available for modules after kernel init. Signed-off-by: Joshua Coombs <josh.coombs@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
*	clk: mvebu: armada 370/XP add clock gating control provider for DT	Gregory CLEMENT	2012-11-20	1	-1/+73
\| \| \| \| \| \|	Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*	clk: mvebu: add clock gating control provider for DT	Sebastian Hesselbarth	2012-11-20	5	-0/+204
\| \| \| \| \| \| \| \| \|	This driver allows to provide DT clocks for clock gates found on Marvell Dove and Kirkwood SoCs. The clock gates are referenced by the phandle index of the corresponding bit in the clock gating control register to ease lookup in the datasheet. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*	clk: mvebu: add armada-370-xp CPU specific clocks	Gregory CLEMENT	2012-11-20	5	-0/+214
\| \| \| \| \| \| \| \|	Add Armada 370/XP specific CPU clocks Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
*	clk: mvebu: add mvebu core clocks.	Sebastian Hesselbarth	2012-11-20	5	-0/+720
	This driver allows to provide DT clocks for core clocks found on Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and ratios are determined by decoding the Sample-At-Reset registers. Although technically correct, using a divider of 0 will lead to div_by_zero panic. Let's use a ratio of 0/1 instead to fail later with a zero clock. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>