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Author
Files
Lines
2017-04-12
clk: aggregate return codes of notify chains
Peter De Schrijver
1
-0
/
+2
2017-04-12
clk: add clk_possible_parents debugfs file
Peter De Schrijver
1
-0
/
+32
2017-04-12
clk: imx: correct uart4_serial clock name in driver for i.MX6UL
Robin van der Gracht
1
-1
/
+1
2017-04-12
clk: zte: Mark pll config tables as const
Stephen Boyd
1
-2
/
+2
2017-04-12
clk: zte: add pll_vga clock for zx296718
Shawn Guo
1
-0
/
+24
2017-04-12
clk: zte: pd_bit is not 0 on zx296718
Shawn Guo
2
-2
/
+16
2017-04-12
clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks
Shawn Guo
1
-3
/
+3
2017-04-12
clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clock
Robin van der Gracht
1
-4
/
+5
2017-04-12
cs-2000-cp: keep Reserved bit on each register
Kuninori Morimoto
1
-3
/
+22
2017-04-12
clk: qcom: msm8996: Fix the vfe1 powerdomain name
Rajendra Nayak
1
-1
/
+1
2017-04-12
clk: stm32f4: fix timeout management for pll and ready gate
Gabriel Fernandez
1
-14
/
+29
2017-04-12
clk: iproc: Remove redundant check
Ray Jui
1
-1
/
+1
2017-04-12
clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
Gabriel Fernandez
1
-3
/
+10
2017-04-12
clk: hi6220: add debug APB clock
Leo Yan
2
-1
/
+5
2017-04-07
clk: meson: mpll: use 64bit math in rate_from_params
Martin Blumenstingl
1
-1
/
+1
2017-04-07
clk: meson: mpll: fix division by zero in rate_from_params
Martin Blumenstingl
1
-11
/
+15
2017-04-07
clk: meson: gxbb: add cts_i958 clock
Jerome Brunet
2
-1
/
+23
2017-04-07
clk: meson: gxbb: add cts_mclk_i958
Jerome Brunet
2
-1
/
+56
2017-04-07
clk: meson: gxbb: add cts_amclk
Jerome Brunet
2
-1
/
+71
2017-04-07
clk: meson: add audio clock divider support
Jerome Brunet
3
-1
/
+155
2017-04-07
clk: meson: gxbb: protect against holes in the onecell_data array
Jerome Brunet
1
-0
/
+4
2017-04-07
MAINTAINERS: Add maintainers for the meson clock driver
Jerome Brunet
1
-0
/
+10
2017-04-04
clk: meson-gxbb: Add GXL/GXM GP0 Variant
Neil Armstrong
2
-28
/
+275
2017-04-04
clk: meson-gxbb: Add GP0 PLL init parameters
Neil Armstrong
1
-0
/
+13
2017-04-04
clk: meson: Add support for parameters for specific PLLs
Neil Armstrong
2
-2
/
+74
2017-04-04
clk: meson-gxbb: Add MALI clocks
Neil Armstrong
1
-0
/
+139
2017-04-04
dt-bindings: clock: gxbb-clkc: Add GXL compatible variant
Neil Armstrong
1
-1
/
+2
2017-04-04
clk: meson-gxbb: Expose GP0 dt-bindings clock id
Neil Armstrong
2
-1
/
+2
2017-04-04
clk: meson-gxbb: Add MALI clock IDS
Neil Armstrong
2
-1
/
+13
2017-04-04
dt-bindings: clk: gxbb: expose i2s output clock gates
Jerome Brunet
2
-5
/
+10
2017-04-04
clk: tegra: Don't reset PLL-CX if it is already enabled
Jon Hunter
1
-4
/
+4
2017-04-04
clk: tegra: Add missing Tegra210 clocks
Peter De Schrijver
4
-8
/
+27
2017-04-04
clk: tegra: Propagate clk_out_x rate to parent
Alex Frid
1
-2
/
+4
2017-03-30
clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0
Geert Uytterhoeven
1
-11
/
+27
2017-03-30
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
Geert Uytterhoeven
1
-50
/
+151
2017-03-30
clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions
Geert Uytterhoeven
1
-0
/
+7
2017-03-30
clk: renesas: cpg-mssr: Add support for fixing up clock tables
Geert Uytterhoeven
2
-0
/
+72
2017-03-27
clk: meson: mpll: correct N2 maximum value
Jerome Brunet
1
-1
/
+1
2017-03-27
clk: meson8b: add the mplls clocks 0, 1 and 2
Jerome Brunet
2
-1
/
+122
2017-03-27
clk: meson: gxbb: mpll: use rw operation
Jerome Brunet
1
-3
/
+3
2017-03-27
clk: meson: mpll: add rw operation
Jerome Brunet
3
-6
/
+180
2017-03-27
clk: gxbb: put dividers and muxes in tables
Jerome Brunet
1
-8
/
+20
2017-03-27
clk: meson8b: put dividers and muxes in tables
Jerome Brunet
1
-4
/
+18
2017-03-27
clk: meson: add missing const qualifiers on gate arrays
Jerome Brunet
2
-2
/
+2
2017-03-27
clk: meson: fix SET_PARM macro
Jerome Brunet
1
-1
/
+1
2017-03-22
clk: rockchip: add pll_wait_lock for pll_enable
Elaine Zhang
1
-0
/
+3
2017-03-22
clk: rockchip: rename RK1108 to RV1108
Andy Yan
5
-226
/
+226
2017-03-22
dt-bindings: rk1108-cru: rename RK1108 to RV1108
Andy Yan
1
-6
/
+6
2017-03-21
clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0
Geert Uytterhoeven
1
-0
/
+24
2017-03-21
clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
Geert Uytterhoeven
4
-4
/
+6
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