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path: root/drivers/clk/qcom/clk-rcg.h (follow)
Commit message (Expand)AuthorAgeFilesLines
* clk: qcom: rcg2: Make hw_clk_ctrl toggleableKonrad Dybcio2023-05-271-0/+2
* clk: qcom: clk-rcg2: add rcg2 mux opsChristian Marangi2022-09-271-0/+1
* clk: qcom: rcg2: Cache CFG register updates for parked RCGsBjorn Andersson2022-05-191-0/+2
* clk: qcom: clk-rcg: add clk_rcg_floor_ops opsAnsuel Smith2022-03-081-0/+1
* clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbersAngeloGioacchino Del Regno2021-02-141-0/+9
* clk: qcom: rcg2: Add support for display port clock opsTaniya Das2019-12-191-0/+1
* clk: qcom: rcg: update the DFS macro for RCGTaniya Das2019-11-071-1/+1
* clk: qcom: clk-rcg2: Introduce a cfg offset for RCGsTaniya Das2019-02-211-0/+2
* clk: qcom: remove empty lines in clk-rcg.hVinod Koul2019-02-211-3/+0
* clk: qcom: Add support for RCG to register for DFSTaniya Das2018-08-271-0/+11
* clk: qcom: Move frequency table macro to common fileTaniya Das2018-07-071-0/+2
* clk: qcom: Configure the RCGs to a safe source as neededAmit Nischal2018-05-081-12/+5
* clk: qcom: add parent map for regmap muxAbhishek Sahu2017-12-221-10/+0
* clk: qcom: Remove unused RCG opsGeorgi Djakov2017-11-021-3/+0
* clk: qcom: Add rcg ops to return floor value closest to the requested rateRajendra Nayak2016-11-231-0/+1
* clk: qcom: Add gfx3d ping-pong PLL frequency switchingStephen Boyd2015-12-011-0/+1
* clk: qcom: clk-rcg: Add customized clk_ops for DSI RCGsArchit Taneja2015-10-171-0/+3
* clk: qcom: Add support for RCGs with shared branchesGeorgi Djakov2015-09-171-1/+3
* clk: qcom: Allow clk_set_parent() to work on display clocksStephen Boyd2015-09-171-0/+1
* clk: qcom: Introduce parent_map tablesGeorgi Djakov2015-03-241-2/+12
* clk: qcom: Properly change rates for ahbix clockStephen Boyd2015-03-121-0/+1
* clk: qcom: Add support for banked MD RCGsStephen Boyd2014-09-231-2/+4
* clk: qcom: Support bypass RCG configurationStephen Boyd2014-07-161-0/+1
* clk: qcom: Support display RCG clocksStephen Boyd2014-05-291-0/+3
* clk: qcom: Add support for root clock generators (RCGs)Stephen Boyd2014-01-161-0/+159