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* Merge tag 'clk-for-linus' of ↵Linus Torvalds2017-05-102-2/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Sort of on the quieter side this time, which is probably due more to me not catching up as quickly on patch review than anything else. Overall it seems normal though, a few small changes to the core, mostly small non-critical fixes here and there as well as driver updates for new and existing hardware support. The biggest things are the TI clk driver rework to lay the groundwork for clkctrl support in the next merge window and the AmLogic audio/graphics clk support. Core: - clk_possible_parents debugfs file so we know which parents a clk could possibly have - Fix to make clk rate change notifiers stop on the first failure instead of continuing New Drivers: - Mediatek MT6797 SoCs - hi655x PMIC clks - AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks - Allwinner H5 SoCs and PRCM hardware Updates: - Nvidia Tegra T210 cleanups and non-critical fixes - TI OMAP cleanups in preparation for clkctrl support - trivial fixes like kcalloc(), devm_* conversions, and seq_puts() - ZTE zx296718 SoC VGA clks - Rockchip clk-ids, fixups, and rename of rk1108 to rv1108 - IDT VersaClock 5P49V5935 support - Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3 support" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (151 commits) clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL clk: ti: divider: try to fix ti_clk_register_divider clk: mvebu: Use kcalloc() in two functions clk: mvebu: Use kcalloc() in of_cpu_clk_setup() clk: nomadik: Delete error messages for a failed memory allocation in two functions clk: nomadik: Use seq_puts() in nomadik_src_clk_show() clk: Improve a size determination in two functions clk: Replace four seq_printf() calls by seq_putc() clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe() clk: si5351: Use devm_kcalloc() in si5351_i2c_probe() clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics() reset: mediatek: Add MT2701 ethsys reset controller include file clk: mediatek: add mt2701 ethernet reset clk: hi6220: Add the hi655x's pmic clock clk: ti: fix building without legacy omap3 clk: ti: fix linker error with !SOC_OMAP4 clk: hi3620: Fix a typo in one variable name clk: hi3620: Delete error messages for a failed memory allocation in two functions clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init() clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init() ...
| * clk: qcom: add parent for venus core0 and core1 gdsc'sStanimir Varbanov2017-04-191-0/+2
| | | | | | | | | | | | | | Make venus_gdsc parent of venus gdsc core0 and core1. Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: clk-smd-rpm: fix rate for branch clks during handoffSrinivas Kandagatla2017-04-191-1/+1
| | | | | | | | | | | | | | | | | | rpm branch clk rate should requested as either 0 or 1 but not INT_MAX. This patch fixes rate request for branch clocks during clk handoff. Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: msm8996: Fix the vfe1 powerdomain nameRajendra Nayak2017-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | Fix a typo which caused both vfe0 and vfe1 powerdomains to be named as vfe0. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Fixes: 7e824d507909 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | scripts/spelling.txt: add regsiter -> register spelling mistakeStephen Boyd2017-05-091-1/+1
|/ | | | | | | | | | This typo is quite common. Fix it and add it to the spelling file so that checkpatch catches it earlier. Link: http://lkml.kernel.org/r/20170317011131.6881-2-sboyd@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* clk: qcom: Do not drop device node twiceGuenter Roeck2017-02-161-1/+0
| | | | | | | | | | | of_find_node_by_name() drops the reference to a passed device node. It is not necessary to drop it again, and doing so may result in the device node being released prematurely. Cc: Rob Herring <robh@kernel.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Fixes: ee15faffef11 ("clk: qcom: common: Add API to register board clocks backwards compatibly") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: SDHCI enablement on Nexus 5X / 6PJeremy McNicoll2017-01-271-0/+18
| | | | | | | | Add missing clock branch to enable onboard storage for msm899(2/4). Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: gdsc: Fix handling of hw control enable/disableRajendra Nayak2017-01-271-13/+45
| | | | | | | | | | | | | | | | | | | | | Once a gdsc is brought in and out of HW control, there is a power down and up cycle which can take upto 1us. Polling on the gdsc status immediately after the hw control enable/disable can mislead software/firmware to belive the gdsc is already either on or off, while its yet to complete the power cycle. To avoid this add a 1us delay post a enable/disable of HW control mode. Also after the HW control mode is disabled, poll on the status to check gdsc status reflects its 'on' before force disabling it in software. Reported-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Reviewed-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Tested-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Fixes: 904bb4f5c7de ("clk: qcom: gdsc: Add support for gdscs with HW control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: mdm9615: Add EBI2 clockZoran Markovic2017-01-101-0/+30
| | | | | | | | | | | | | | | | | | | Add definition of EBI2 clock used by MDM9615 NAND controller. Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> [sboyd@codeaurora.org: ebi2_clk halt bit is 24 not 23] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Add GCC_MSS_RESET supportAvaneesh Kumar Dwivedi2017-01-101-0/+1
| | | | | | | | | Add support to use reset control framework for resetting MSS with hexagon v56 1.5.0. Signed-off-by: Avaneesh Kumar Dwivedi <akdwived@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
*-. Merge branches 'clk-qcom-rpm8974', 'clk-stm32f4', 'clk-ipq4019' and ↵Stephen Boyd2017-01-102-14/+536
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-fixes' into clk-next * clk-qcom-rpm8974: clk: qcom: smd-rpmcc: Add msm8974 clocks * clk-stm32f4: clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board clk: stm32f4: Add SAI clocks clk: stm32f4: Add I2S clock clk: stm32f4: Add lcd-tft clock clk: stm32f4: Add post divisor for I2S & SAI PLLs clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards clk: stm32f4: Update DT bindings documentation * clk-ipq4019: clk: qcom: ipq4019: Add the cpu clock frequency change notifier clk: qcom: ipq4019: Add all the frequencies for apss cpu clk: qcom: ipq4019: correct sdcc frequency and parent name clk: qcom: ipq4019: Add the nodes for pcnoc clk: qcom: ipq4019: Add the apss cpu pll divider clock node clk: qcom: ipq4019: remove fixed clocks and add pll clocks * clk-fixes: clk: stm32f4: Use CLK_OF_DECLARE_DRIVER initialization method clk: renesas: mstp: Support 8-bit registers for r7s72100
| | * clk: qcom: ipq4019: Add the cpu clock frequency change notifierAbhishek Sahu2016-12-271-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current driver code gives the crash or gets hang while switching the CPU frequency some time. The APSS CPU Clock divider is not glitch free so it the APPS clock need to be switched for stable clock during the change. This patch adds the frequency change notifier for APSS CPU clock. It changes the parent of this clock to stable PLL FEPLL500 for PRE_RATE_CHANGE event. This event will be generated before actual clock set operations. The clock set operation will again change its corresponding parent by getting the same from frequency table. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> [sboyd@codeaurora.org: Indent less in probe] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: qcom: ipq4019: Add all the frequencies for apss cpuAbhishek Sahu2016-12-221-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | The APSS CPU clock does not contain all the frequencies in its frequency table so this patch adds the same. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: qcom: ipq4019: correct sdcc frequency and parent nameAbhishek Sahu2016-12-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | 1. The parent for sdcc clock is sdccpll. 2. The frequency value was wrong so modified the same. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: qcom: ipq4019: Add the nodes for pcnocAbhishek Sahu2016-12-221-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ipq4019 clock driver does not have the node for PCNOC so this patch adds and registers the PCNOC clock nodes. This PCNOC clock is critical and should not be turned off so setting CRITICAL flag also. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: qcom: ipq4019: Add the apss cpu pll divider clock nodeAbhishek Sahu2016-12-221-0/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ipq4019 clock driver does not have support for all the frequency supported by APSS CPU. APSS CPU frequency is provided with APSS CPU PLL divider which divides down the VCO frequency. This divider is nonlinear and specific to IPQ4019 so the standard divider code cannot be used for this. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| | * clk: qcom: ipq4019: remove fixed clocks and add pll clocksAbhishek Sahu2016-12-221-11/+243
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ipq4019 clock driver registered the PLL clocks and dividers as fixed clock. These fixed clock needs to be removed from driver probe function and same need to be registered with clock framework. These PLL clocks should be programmed only once and the same are being programmed already by the boot loader so the set rate operation is not required for these clocks. Only the rate can be calculated by clock operations in clock driver file so this patch adds the same. The PLL takes the reference clock from XO and generates the intermediate VCO frequency. This VCO frequency will be divided down by different PLL internal dividers. Some of the PLL internal dividers are fixed while other are programmable. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: smd-rpmcc: Add msm8974 clocksBjorn Andersson2016-12-221-0/+71
|/ | | | | | | | | | This adds all RPM based clocks for msm8974, except cxo and gfx3d_clk_src. Tested-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Put venus core0/1 gdscs to hw control modeSricharan R2016-11-241-0/+2
| | | | | | | | | | | The venus video ip's internal core blocks are under the control of the firmware and their powerdomains needs to be 'ON' only when used by the firmware. So putting it into hw controlled mode lets this to happen, otherwise the firmware hangs checking for this. Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: gdsc: Add support for gdscs with HW controlRajendra Nayak2016-11-242-0/+19
| | | | | | | | | | | | Some GDSCs might support a HW control mode, where in the power domain (gdsc) is brought in and out of low power state (while unsued) without any SW assistance, saving power. Such GDSCs can be configured in a HW control mode when powered on until they are explicitly requested to be powered off by software. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: clk-rpm: Fix clk_hw referencesGeorgi Djakov2016-11-231-14/+22
| | | | | | | | | Fix the clk_hw references to the actual clocks and add a xlate function to return the hw pointers from the already existing static array. Reported-by: Michael Scott <michael.scott@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: clk-smd-rpm: Fix clk_hw referencesGeorgi Djakov2016-11-231-14/+22
| | | | | | | | | Fix the clk_hw references to the actual clocks and add a xlate function to return the hw pointers from the already existing static array. Reported-by: Michael Scott <michael.scott@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_opsRajendra Nayak2016-11-235-18/+18
| | | | | | | | | | | | | | The sdcc driver for msm8996/msm8916/msm8974/msm8994 and apq8084 expects a clk_set_rate() on the sdcc rcg clk to set a floor value of supported clk rate closest to the requested rate, by looking up the frequency table. So move all the sdcc rcgs on all these platforms to use the newly introduced clk_rcg2_floor_ops Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Add rcg ops to return floor value closest to the requested rateRajendra Nayak2016-11-234-9/+86
| | | | | | | | | | | | | | | The default behaviour with clk_rcg2_ops is for the clk_round_rate()/clk_set_rate() to return/set a ceil clock rate closest to the requested rate by looking up the corresponding frequency table. However, we do have some instances (mainly sdcc on various platforms) of clients expecting a clk_set_rate() to set a floor value instead. Add a new clk_rcg2_floor_ops to handle this for such specific rcg instances Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge branch 'clk-qcom-rpm' into clk-nextStephen Boyd2016-11-115-9/+1096
|\ | | | | | | | | | | | | * clk-qcom-rpm: clk: qcom: Add support for RPM Clocks clk: qcom: Add support for SMD-RPM Clocks clk: qcom: Always add factor clock for xo clocks
| * clk: qcom: Add support for RPM ClocksGeorgi Djakov2016-11-113-0/+503
| | | | | | | | | | | | | | | | | | | | | | This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_rpm driver to communicate with RPM. Such platforms are apq8064 and msm8960. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Add support for SMD-RPM ClocksGeorgi Djakov2016-11-113-0/+587
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_smd_rpm driver to communicate with RPM. Such platforms are msm8916, apq8084 and msm8974. The RPM is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power profile. It communicates with other hardware subsystems via shared memory and accepts clock requests, aggregates the requests and turns the clocks on/off or scales them on demand. This driver is based on the codeaurora.org driver: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Rob Herring <robh@kernel.org> [sboyd@codeaurora.org: Remove useless braces for single line if] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: qcom: Always add factor clock for xo clocksGeorgi Djakov2016-11-111-9/+6
| | | | | | | | | | | | | | | | | | | | Currently the RPM/RPM-SMD clock drivers do not register the xo clocks, so we should always add factor clock. When we later add xo clocks support into the drivers, we should update this function to skip registration. By doing so we avoid any DT dependencies. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge branch 'clk-qcom-8994' into clk-nextStephen Boyd2016-11-113-0/+2309
|\ \ | | | | | | | | | | | | | | | * clk-qcom-8994: clk: qcom: Add support for msm8994 global clock controller dt-bindings: qcom: clocks: Add msm8994 clock bindings
| * | clk: qcom: Add support for msm8994 global clock controllerBastian Köcher2016-11-113-0/+2309
| |/ | | | | | | | | | | | | | | | | | | | | The clock definition was ported from the Google 3.10 kernel tree to work with the latest kernel. Signed-off-by: Bastian Köcher <mail@kchr.de> [jeremymc@redhat.com: created new commit of just dt-bindings] Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> [sboyd@codeaurora.org: Tidy up commit text and Kconfig help] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: ipq806x: Fix board clk ratesStephen Boyd2016-11-101-2/+2
| | | | | | | | | | | | | | | | | | The clocks on these boards run at 25 MHz, not 19.2 and 27 like other platforms. Unfortunately I copy/pasted from other similar SoCs but forgot this one is different. Fix it. Fixes: a085f877a882 ("clk: qcom: Move cxo/pxo/xo into dt files") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: Add freq tables for a few rcgsRajendra Nayak2016-11-021-0/+25
| | | | | | | | | | | | | | Add frequency tables for a few RCG clocks in msm8996 Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: Add .is_enabled ops for clk-alpha-pllRajendra Nayak2016-11-021-0/+26
| | | | | | | | | | | | | | | | | | This would be useful in subsequent patches when the .set_rate operation would need to identify if the PLL is actually enabled Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Simplify return statement of is_enabled op] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: Enable FSM mode for votable alpha PLLsRajendra Nayak2016-11-025-28/+38
| | | | | | | | | | | | | | | | | | | | | | The votable alpha PLLs need to have the fsm mode enabled as part of the initialization. The sequence seems to be the same as used by clk-pll, so move the function which does this into a common place and reuse it for the clk-alpha-pll Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: handle alpha PLLs with 16bit alpha val registersRajendra Nayak2016-11-022-7/+18
| | | | | | | | | | | | | | | | | | Some alpha PLLs have support for only a 16bit programable Alpha Value (as against the default 40bits). Add a flag to handle the 16bit alpha registers Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: Add support to initialize alpha pllsRajendra Nayak2016-11-022-0/+51
| | | | | | | | | | | | | | Add a function to do initial configuration of the alpha plls Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: Add support for alpha pll hwfsm opsRajendra Nayak2016-11-022-12/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some PLLs can support an HW FSM mode (different from the Votable FSMs, though its the same bit used to enable Votable FSMs as well as HW FSMs) which enables the HW to do the bypass/reset/enable-output-ctrl sequence on its own. So all thats needed from SW is to set the FSM_ENA bit. PLL_ACTIVE_FLAG is whats used to check if the PLL is active/enabled. Some of the PLLs which support HW FSM can also need an OFFLINE request that needs to be toggled across the enable/disable. We use a flag to identify such cases and handle them. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: ipq4019: changed i2c freq tableAbhishek Sahu2016-11-021-2/+1
| | | | | | | | | | | | | | | | | | | | The current I2C freq table uses MND values which is not applicable for I2C since its RCG does not have MND counter. This patch updates the freq table for 19.05 MHz clk frequency with FEPLL_200 parent. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: lcc-ipq806x: Fixup overriding val in regmap_read callAxel Lin2016-11-021-1/+1
| | | | | | | | | | | | | | | | Drop the assignment of regmap_read return code to val, so the code checks the value read. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: mmcc-8996: Add gpu gdscsRajendra Nayak2016-11-021-0/+24
| | | | | | | | | | | | | | Add gpu gdsc data for msm8996 Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: Handle the clamp_io assert/deassert sequenceRajendra Nayak2016-11-022-1/+27
|/ | | | | | | | Add a flag to mark gdscs which need to support the clamp deassert/assert before and after the gdsc enable/disable Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: Add USB3 PHY reset linesVivek Gautam2016-09-171-0/+2
| | | | | | | Adding missing reset lines for USB 3.0 PHY. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: gcc-msm8996: add missing pcie phy reset linesSrinivas Kandagatla2016-08-251-0/+2
| | | | | | | This patch adds missing 2 PCIE common reset lines. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: gcc-msm8996: Fix pcie 2 pipe register offsetSrinivas Kandagatla2016-08-251-2/+2
| | | | | | | | | This patch corrects the register offset for pcie2 pipe clock. Offset according to datasheet is 0x6e018 instead of 0x6e108. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: select GDSC for msm8996 gcc and mmccSrinivas Kandagatla2016-08-251-0/+2
| | | | | | | | | | | | | This patch selects QCOM_GDSC Kconfig for msm8996 GCC and MMCC clock controllers, as these provide some of the gdscs on the SOC. Also selecting this config will make it align with other drivers which do the same. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 52111672f791 ("clk: qcom: gdsc: Add GDSCs in msm8996 GCC") Fixes: 7e824d507909 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Migrate to clk_hw based registration and OF APIsStephen Boyd2016-08-256-45/+47
| | | | | | | | | Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers in this driver, allowing us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: gdsc: Add the missing BIMC gdsc for msm8996Rajendra Nayak2016-08-191-0/+9
| | | | | | | Add BIMC gdsc data found in MMCC part of msm8996 family of devices. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: gcc-ipq4019: Delete unnecessary assignment for the field "owner"Markus Elfring2016-08-171-1/+0
| | | | | | | | | The field "owner" is set by the core. Thus delete an unneeded initialisation. Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: Sort Makefile alphabeticallyStephen Boyd2016-08-161-3/+4
| | | | | | We've started getting out of order, fix it. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: mdm9615: Add support for MDM9615 Clock ControllersNeil Armstrong2016-08-164-0/+2326
| | | | | | | | In order to support the Qualcomm MDM9615 SoC, add support for the Global and LPASS Clock Controllers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 19:13:58 +0100