linux - linux

	Commit message (Expand)	Author	Age	Files	Lines
*	clk: renesas: r8a7796: Add CPEX clock	Geert Uytterhoeven	2018-12-04	1	-0/+1
*	Merge branch 'clk-renesas' into clk-next	Stephen Boyd	2018-10-19	1	-33/+34
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\| *	clk: renesas: r8a7796: Add OSC EXTAL predivider configuration	Geert Uytterhoeven	2018-08-27	1	-33/+33
\| *	clk: renesas: rcar-gen3: Rename rint to .r	Geert Uytterhoeven	2018-08-27	1	-1/+2
* \|	clk: renesas: use SPDX identifier for Renesas drivers	Wolfram Sang	2018-08-31	1	-4/+1
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*	clk: renesas: r8a7796: Add Z2 clock	Takeshi Kihara	2018-02-12	1	-0/+1
*	clk: renesas: r8a7796: Add Z clock	Takeshi Kihara	2018-02-12	1	-0/+1
*	clk: renesas: r8a7796: Add FDP clock	ABE Hiroshige	2018-01-05	1	-0/+1
*	clk: renesas: r8a7796: Correct parent clock of INTC-AP	Geert Uytterhoeven	2017-10-16	1	-1/+1
*	clk: renesas: r8a7796: Add USB3.0 clock	Hiromitsu Yamasaki	2017-08-17	1	-0/+1
*	clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3	Geert Uytterhoeven	2017-08-16	1	-17/+17
*	clk: renesas: r8a7796: Add INTC-EX clock	Takeshi Kihara	2017-05-15	1	-0/+1
*	clk: renesas: r8a7796: Add PCIe clocks	Harunobu Kurokawa	2017-05-15	1	-0/+2
*	clk: renesas: r8a7796: Add PWM clock	Ryo Kodama	2017-05-15	1	-0/+1
*	clk: renesas: r8a7796: Add HS-USB clock	Kazuya Mizuguchi	2017-05-15	1	-0/+1
*	clk: renesas: r8a7796: Add Sound DVC clocks	Kazuya Mizuguchi	2017-05-15	1	-0/+2
*	clk: renesas: r8a7796: Add Sound SRC clock	Kazuya Mizuguchi	2017-05-15	1	-0/+13
*	clk: renesas: r8a7796: Add Sound SSI clock	Kazuya Mizuguchi	2017-05-15	1	-0/+11
*	clk: renesas: r8a7796: Add USB-DMAC clocks	Hiromitsu Yamasaki	2017-05-15	1	-0/+2
*	clk: renesas: r8a7796: Add Audio-DMAC clocks	Hiromitsu Yamasaki	2017-05-15	1	-0/+2
*	clk: renesas: r8a7796: Add EHCI/OHCI clocks	Kazuya Mizuguchi	2017-05-15	1	-0/+2
*	clk: renesas: r8a7796: Add HDMI clock	Koji Matsuoka	2017-05-15	1	-0/+2
*	clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()	Geert Uytterhoeven	2017-03-21	1	-1/+1
*	clk: renesas: r8a7796: Reformat core clock table	Geert Uytterhoeven	2017-03-21	1	-6/+6
*	clk: renesas: r8a7796: Correct name of watchdog clock	Geert Uytterhoeven	2017-03-21	1	-1/+1
*	clk: renesas: r8a7796: Add IMR clocks	Sergei Shtylyov	2017-03-06	1	-0/+2
*	clk: renesas: r8a7796: Add IIC-DVFS clock	Khiem Nguyen	2017-01-27	1	-0/+1
*	clk: renesas: r8a7796: Add MSIOF controller clocks	Hiromitsu Yamasaki	2016-12-27	1	-0/+5
*	clk: renesas: r8a7796: Add CAN FD peripheral clock	Chris Paterson	2016-12-27	1	-0/+1
*	clk: renesas: r8a7796: Add CANFD clock	Chris Paterson	2016-12-27	1	-0/+1
*	clk: renesas: r8a7796: Add CAN peripheral clock	Chris Paterson	2016-12-27	1	-0/+2
*	clk: renesas: r8a7796: Add VIN clocks	Niklas Söderlund	2016-11-07	1	-0/+8
*	clk: renesas: r8a7796: Add CSI2 clocks	Niklas Söderlund	2016-11-07	1	-0/+4
*	Merge branch 'rcar-rst' into clk-renesas-for-v4.10	Geert Uytterhoeven	2016-11-02	1	-1/+7
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\| *	clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driver	Geert Uytterhoeven	2016-11-02	1	-1/+7
* \|	clk: renesas: r8a7796: Add DU and LVDS clocks	Laurent Pinchart	2016-11-02	1	-0/+4
* \|	clk: renesas: r8a7796: Add VSP clocks	Laurent Pinchart	2016-11-02	1	-0/+5
* \|	clk: renesas: r8a7796: Add FCP clocks	Laurent Pinchart	2016-11-02	1	-0/+8
* \|	clk: renesas: r8a7796: Add DRIF clock	Ramesh Shanmugasundaram	2016-11-02	1	-0/+8
* \|	clk: renesas: r8a7796: Add I2C clocks	Ulrich Hecht	2016-10-17	1	-0/+7
* \|	clk: renesas: r8a7796: Add HSCIF clocks	Ulrich Hecht	2016-10-17	1	-0/+5
* \|	clk: renesas: r8a7796: Add SCIF clocks	Ulrich Hecht	2016-10-17	1	-0/+5
* \|	clk: renesas: r8a7796: Add SYS-DMAC clocks	Ulrich Hecht	2016-10-17	1	-0/+3
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*	clk: renesas: r8a7796: Add CMT clocks	Bui Duc Phuc	2016-09-12	1	-0/+4
*	clk: renesas: r8a7796: Add RAVB clock	Laurent Pinchart	2016-09-12	1	-0/+1
*	clk: renesas: r8a7796: Add THS/TSC clock	Khiem Nguyen	2016-09-05	1	-0/+1
*	clk: renesas: r8a7796: Add SDIF clocks	Simon Horman	2016-08-23	1	-0/+10
*	clk: renesas: r8a7796: Add GPIO clocks	Takeshi Kihara	2016-08-19	1	-0/+8
*	clk: renesas: r8a7796: Add watchdog module clock	Geert Uytterhoeven	2016-08-09	1	-0/+1
*	clk: renesas: r8a7796: Add watchdog core clocks	Geert Uytterhoeven	2016-08-09	1	-0/+6