| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | clk: renesas: rcar-gen3: Mark RWDT clocks as critical | Ulrich Hecht | 2020-06-22 | 1 | -1/+1 |
| * | clk: renesas: r8a77970: Add CPEX clock | Geert Uytterhoeven | 2018-12-04 | 1 | -0/+1 |
| * | clk: renesas: r8a77970: Add RPC clocks | Sergei Shtylyov | 2018-11-05 | 1 | -0/+4 |
| * | Merge branch 'clk-renesas' into clk-next | Stephen Boyd | 2018-10-19 | 1 | -2/+74 |
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| | * | clk: renesas: r8a77970: Add TPU clock | Sergei Shtylyov | 2018-09-25 | 1 | -0/+1 |
| | * | clk: renesas: r8a77970: Add TMU clocks | Sergei Shtylyov | 2018-09-11 | 1 | -0/+5 |
| | * | clk: renesas: r8a77970: Add CMT clocks | Sergei Shtylyov | 2018-09-11 | 1 | -0/+4 |
| | * | clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI | Sergei Shtylyov | 2018-09-03 | 1 | -2/+64 |
| * | | clk: renesas: Convert to SPDX identifiers | Kuninori Morimoto | 2018-09-29 | 1 | -4/+1 |
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| * | clk: renesas: r8a77970: Add LVDS clock | Sergei Shtylyov | 2017-12-08 | 1 | -0/+1 |
| * | clk: renesas: cpg-mssr: Add R8A77970 support | Sergei Shtylyov | 2017-09-19 | 1 | -0/+199 |
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